A control circuit includes a first output unit configured to output a constant bias current for setting an electrical bias state of a bias circuit to the bias circuit; a second output unit configured to output a bias control current or constant voltage for controlling the electrical bias state of the bias circuit to the bias circuit; a resistor having one end connected to a reference potential; and a switch provided between another end of the resistor and an output terminal of the second output unit.

In a semiconductor device including gate fingers each having a linear shape extending from a feed line, and arranged in areas between drain electrodes and source electrodes, open stubs are connected directly to the feed line.

A microwave amplifier having a load network which provides more efficient amplification of a low power microwave frequency signal. The amplifier comprises a transistor and a load network coupled to the transistor output to shape a waveform of an amplified microwave signal at the transistor current source plane. The load network comprises: a fundamental matching network to provide impedance matching at a fundamental frequency; a half-wave transmission line for a second harmonic frequency disposed between the transistor output and the fundamental matching network; a quarter-wave stub and a five-quarter-wave stub for a third harmonic frequency arranged on the half-wave transmission line to provide an open circuit condition at the third harmonic; and a quarter-wave stub for the second harmonic frequency and a quarter-wave stub for the fundamental frequency, arranged on the half-wave transmission line to provide a short circuit condition at the second harmonic frequency.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

An amplifier device comprises an amplifying unit and a bias module. The amplifying unit has a first end coupled to a voltage source configured to receive a source voltage, a second end configured to receive an input signal, and a third end coupled to a first reference potential terminal configured to receive a first reference potential. The first end of the amplifying unit is configured to output an output signal amplified by the amplifying unit. The bias module is coupled to the second end of the amplifying unit, and configured to receive a voltage signal to provide a bias current to the amplifying unit. The voltage signal is a variable voltage. A supply current flowing into the amplifying unit and is adjusted in accordance with the voltage signal to stay within a predetermined range.

An amplifier device comprises an amplifying unit and a bias module. The amplifying unit has a first end coupled to a voltage source configured to receive a source voltage, a second end configured to receive an input signal, and a third end coupled to a first reference potential terminal configured to receive a first reference potential. The first end of the amplifying unit is configured to output an output signal amplified by the amplifying unit. The bias module is coupled to the second end of the amplifying unit, and configured to receive a voltage signal to provide a bias current to the amplifying unit. The voltage signal is a variable voltage. A supply current flowing into the amplifying unit and is adjusted in accordance with the voltage signal to stay within a predetermined range.

Bias networks for amplifiers are disclosed. An example bias network includes an adaptive bias circuit, configured to generate a bias signal for an amplifier, and further includes a coupling circuit, configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is made adaptive in that its' impedance depends on a power level of an input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit may adapt to the input power level and, thereby, may modify the bias signal to reduce/optimize at least some of the nonlinearity that may be introduced to the bias signal by the adaptive bias circuit.