A class D amplifier including a pulse width modulation (PWM) control loop, an H-bridge driver, a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop, and a comparator. The comparator is configured to trigger a cutoff of a PWM pulse generated by the PWM pulse generator during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.

A class D amplifier including a pulse width modulation (PWM) control loop, an H-bridge driver, a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop, and a comparator. The comparator is configured to trigger a cutoff of a PWM pulse generated by the PWM pulse generator during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.

In some embodiments, an audio amplifier can include an input node for receiving a digital signal, and a controller coupled to the input node through a feed-forward path. The controller can be configured to generate a driving signal based on the digital signal. The audio amplifier can further include a driver configured to provide an amplified signal at an output node based on the driving signal, and a feedback circuit that couples the output node of the driver to the controller. The feedback circuit can be configured to provide a feedback signal for comparison with a reference signal representative of the digital signal to generate an error signal, such that the feedback circuit provides a form of the error signal to the controller for adjustment of the digital signal.

In some embodiments, an audio amplifier can include an input node for receiving a digital signal, and a controller coupled to the input node through a feed-forward path. The controller can be configured to generate a driving signal based on the digital signal. The audio amplifier can further include a driver configured to provide an amplified signal at an output node based on the driving signal, and a feedback circuit that couples the output node of the driver to the controller. The feedback circuit can be configured to provide a feedback signal for comparison with a reference signal representative of the digital signal to generate an error signal, such that the feedback circuit provides a form of the error signal to the controller for adjustment of the digital signal.

A switching audio amplifier and method of operation. The switching audio amplifier comprises a voltage supply selector coupling a power supply input to a first power supply voltage; a switching circuit generating a drive signal for a loudspeaker by modulating the power supply input based on a modulation signal; a pulse generator receiving an audio input signal and outputting the modulation signal based on the audio input signal and the voltage of the power supply input; and a supply voltage monitor. The supply voltage monitor is configured to increase the voltage of the power supply input by causing the voltage supply selector to couple the power supply input to a second power supply voltage responsive to the modulation signal exceeding the first threshold, and the supply voltage monitor preventing the voltage supply selector from reducing the voltage of the power supply input for a first time period.

In some embodiments, an audio driver includes an audio amplifier configured to operate in a high output resistance (HOR) mode with an HOR driver or a zero output resistance (ZOR) mode with a ZOR driver, The audio amplifier includes an output node coupled to both of the HOR driver and the ZOR driver, such that the output node is subject to an effect of the ZOR driver in a disabled state when the audio amplifier is operating in the HOR mode. The audio driver further includes a control system configured to correct for the effect of the disabled ZOR driver by adjusting an input signal.

In some embodiments, an audio driver includes an audio amplifier configured to operate in a high output resistance (HOR) mode with an HOR driver or a zero output resistance (ZOR) mode with a ZOR driver, The audio amplifier includes an output node coupled to both of the HOR driver and the ZOR driver, such that the output node is subject to an effect of the ZOR driver in a disabled state when the audio amplifier is operating in the HOR mode. The audio driver further includes a control system configured to correct for the effect of the disabled ZOR driver by adjusting an input signal.

A series-connected delta-sigma modulator (DSM) comprises a first DSM, configured to receive an input signal, comprising a first loop filter, configured to generate a first processed signal; and a first quantizer, coupled to the first loop filter, configured to generate a first quantized signal, and to feed back the first quantized signal to the first loop filter, wherein the first quantized signal comprises a clipping error smaller than a first predetermined value; and a second DSM, coupled to the first DSM, configured to receive the first quantized signal from the first DSM, comprising a second loop filter, configured to generate a second processed signal; and a second quantizer, coupled to the second loop filter, configured to generate a second quantized signal, and to feed back the second quantized signal to the second loop filter, wherein the second quantized signal comprises a quantization error smaller than a second predetermined value.

An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.

An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.