A switching amplifier system includes an amplifier printed circuit board (PCB); a filter PCB coupled to the amplifier PCB and configured to receive an amplified signal from the amplifier PCB, and a resonant capacitor PCB coupled to the filter PCB and to one or more antennas The resonant capacitor PCB is physically separated from the amplifier PCB and the filter PCB by a distance of at least 10 mm. The filter PCB is physically separated from the amplifier PCB by a distance of at least 10 mm.

The present invention suppresses unevenness of an input/output current of a full bridge circuit, which is caused due to a cross current generated by a delay operation or the like of a switching element and unevenness of a driver voltage of each switching element, and suppresses an occurrence of an erroneous operation of an amplifier of a class-D full bridge circuit. A driver device of a class-D full bridge amplifier according to the present invention sets, at the same potential in terms of DC, reference potentials on a low-voltage side of two high-side driver circuits which drive two high-side switching elements which constitute a full bridge circuit, and suppresses an occurrence of unevenness of a driver voltage of the switching elements due to a cross current which flows between the bridge circuit and the high-side driver circuits. In the configuration in which a plurality of class-D full bridge amplifiers are driven, a driver power supply is individually provided to driver circuits which drive the class-D full bridge amplifiers, and cross currents which flow between the plurality of class-D full bridge amplifiers are suppressed.

The present invention suppresses unevenness of an input/output current of a full bridge circuit, which is caused due to a cross current generated by a delay operation or the like of a switching element and unevenness of a driver voltage of each switching element, and suppresses an occurrence of an erroneous operation of an amplifier of a class-D full bridge circuit. A driver device of a class-D full bridge amplifier according to the present invention sets, at the same potential in terms of DC, reference potentials on a low-voltage side of two high-side driver circuits which drive two high-side switching elements which constitute a full bridge circuit, and suppresses an occurrence of unevenness of a driver voltage of the switching elements due to a cross current which flows between the bridge circuit and the high-side driver circuits. In the configuration in which a plurality of class-D full bridge amplifiers are driven, a driver power supply is individually provided to driver circuits which drive the class-D full bridge amplifiers, and cross currents which flow between the plurality of class-D full bridge amplifiers are suppressed.

Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

An adiabatic resonator, an adiabatic oscillator, and an adiabatic oscillator system are disclosed. An adiabatic system is one that ideally transfers no heat outside of the system, thereby reducing the required operating power. The adiabatic resonator, which includes a plurality of tank circuits, acts as an energy reservoir, the missing aspect of previously attempted adiabatic computational systems. By using the adiabatic resonator as a feedback element with an amplifier, an adiabatic oscillator is formed. An adiabatic oscillator system is formed with a primary adiabatic oscillator feeding a plurality of secondary adiabatic oscillators. In this manner, the adiabatic oscillator system may be used to generate the multiple clock signals required of adiabatic computational logic elements, such as Split-level Charge Recovery Logic and 2-Level Adiabatic Logic. The adiabatic oscillator system stores enough energy to drive many individual adiabatic computational logic elements, permitting implementation of complex logic circuits.

The technology described in this document can be embodied in an apparatus that includes an amplifier that includes a first Zeta converter connected to a power supply and a load. The amplifier also includes a second Zeta converter connected to the power supply and the load. The second Zeta converter is driven by a complementary duty cycle relative to the first Zeta converter. The amplifier also includes a controller to provide an audio signal to the first Zeta converter and the second Zeta converter for delivery to the load.

In some embodiments, a low voltage system can include a capacitor between an output node of an amplifier and ground, with the output node connectable to a load, and the amplifier configured to operate with a series of pulses. The low voltage system can further include a monitoring circuit configured to monitor a voltage at the capacitor against a desired low voltage value, and a control system configured to generate the series of pulses for the amplifier, and to control charging and discharging of the capacitor based on an output of the monitoring circuit to regulate the voltage at the output node at approximately the desired low voltage value.

In some embodiments, a low voltage system can include a capacitor between an output node of an amplifier and ground, with the output node connectable to a load, and the amplifier configured to operate with a series of pulses. The low voltage system can further include a monitoring circuit configured to monitor a voltage at the capacitor against a desired low voltage value, and a control system configured to generate the series of pulses for the amplifier, and to control charging and discharging of the capacitor based on an output of the monitoring circuit to regulate the voltage at the output node at approximately the desired low voltage value.

The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.