An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.

A power encoder includes a pulse width modulator for modulating a signal according to a set of thresholds to produce a pulse width modulated (PWM) signal and a switch mode power amplifier for amplifying the PWM signal by switching states of switching devices according to amplitudes of the PWM signal. At least one or combination of a distribution of values of the voltage thresholds in the set and a distribution of values of a current generated by different switching devices are non-uniform. The set of voltage thresholds includes at least two positive voltage thresholds.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

Embodiments of apparatuses and methods for proportional feedback for reduced overshoot and undershoot in a switched output are described. An embodiment of an apparatus includes a switching output stage configured to receive an input signal and provide a responsive output signal. The apparatus may also include a pulling circuit coupled to one of the first switching device and the second switching device. The pulling circuit may pull a control voltage of power transistors in the switching output stage to reduce impedance of at least one of the transistors in response to a determination that the output signal at the common output node is outside of a predetermined range of a threshold value. Pulling strength may increase as a voltage difference between the output signal and one of the first supply voltage and the second supply voltage increases.

Embodiments of apparatuses and methods for proportional feedback for reduced overshoot and undershoot in a switched output are described. An embodiment of an apparatus includes a switching output stage configured to receive an input signal and provide a responsive output signal. The apparatus may also include a pulling circuit coupled to one of the first switching device and the second switching device. The pulling circuit may pull a control voltage of power transistors in the switching output stage to reduce impedance of at least one of the transistors in response to a determination that the output signal at the common output node is outside of a predetermined range of a threshold value. Pulling strength may increase as a voltage difference between the output signal and one of the first supply voltage and the second supply voltage increases.

The present invention relates to a system and a method for pulse width modulation and demodulation of a continuous input signal, which system is configured to receive a continuous input to an analog modulator, which system comprises a demodulator generating a continuous output signal. It is the object of the pending patent application to use an analog modulator for transmitting the signal from the input stage over to an output stage. A further object of the pending patent application is to preserve the signal integrity in regard to precision and to minimize both non-linearities and distortion side effects. The object can be fulfilled by the analog modulator being formed as a composite phase modulator which composite phase modulator comprises at least one feedback loop which feedback loop determines the width of a low-level discrete signal, which composite phase modulator comprises at least one feed-forward loop, which feed-forward loop determines the width of a high-level discrete signal as a function of the continuous input. Hereby it can be achieved that timing between discrete low-level and high-level forms a discontinuous output signal representing the continuous input.

A power amplifier circuit includes a first amplifier that amplifies a first signal, and a second amplifier arranged subsequent to the first amplifier. The second amplifier amplifies a second signal that is based on an output signal of the first amplifier. The first amplifier performs class inverse-F operation, and the second amplifier performs class F operation.

Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.

A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.