A boost DC-DC power converter comprising a semiconductor switch arrangement comprising a plurality of series connected semiconductor switches. A first capacitor is connected between a first intermediate node of a first leg of the semiconductor switch arrangement and a second intermediate node of a second leg of the semiconductor switch arrangement. A control circuit is coupled to respective control terminals of the plurality of semiconductor switches. A load sensor is configured to detect a load current and/or a load voltage of a load circuit connectable to at least a first DC output voltage of the DC-DC power converter. The control circuit being further configured to adjusting one or more operational parameters of the boost DC-DC power converter based on the detected load current and/or load voltage.

A signal processing system for producing a load voltage at a load output of the signal processing system, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first load voltage and the second load voltage, and may include a first processing path configured to process a first signal derived from an input signal to generate the first load voltage at a first processing path output, a second processing path configured to process a second signal received at a second processing path input and derived from the input signal, wherein the second signal comprises information of the input signal absent from the first signal, to generate the second load voltage at a second processing path output, and a high-pass filter coupled between the first processing path output and the second processing path input.

A method may include processing a first signal derived from an input signal with a first path to generate a first path voltage at a first path output, processing a second signal derived from the input signal with a second path to generate a second path voltage at a second path output, the second path comprising a linear amplifier having at least one transistor for driving the second path voltage, generating the first signal and the second signal with a signal splitter, such that the second signal comprises information of the input signal absent from the first signal, and such that the second path voltage is of a sufficient magnitude such that the at least one transistor operates in a saturation region of the at least one transistor throughout a dynamic range of a load voltage equal to the difference of the first path voltage and the second path voltage.

A system includes an audio amplifier, a duty cycle detector, a channel equalizer, and a sample-and-hold circuit. The audio amplifier is configured to amplify an analog audio signal to produce an amplified audio signal. The duty cycle detector is configured to generate a saturation detect signal at a first state upon detection that the amplified audio signal produced by the audio amplifier is clipped. The channel equalizer is configured to generate an initial estimate of a speaker terminal voltage. The sample-and-hold circuit is configured to sample and hold the initial estimate of the speaker terminal voltage as a final estimate of the speaker voltage when the saturation detect signal is in the first state.

A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.

A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.

Embodiments are directed to modulating a pulse width modulation (PWM) signal, by initializing at least one phase index to an initial value, establishing a set of values in a lookup table that correspond to data points for PWM comparator values that correspond to a given number of samples of a single periodic waveform during a predetermined sampling rate that establishes a table resolution, repeatedly executing the following operations at the predetermined sampling rate: determining a value of a command signal frequency, setting a value to a jump factor equal to the quotient of the value of the command signal frequency divided by the table resolution, progressing the value of the phase index by the value of the jump factor, selecting a value of a commutation vector from the lookup table that corresponds to the phase index, and loading the value of the commutation vector into a corresponding PWM comparator.

Embodiments are directed to modulating a pulse width modulation (PWM) signal, by initializing at least one phase index to an initial value, establishing a set of values in a lookup table that correspond to data points for PWM comparator values that correspond to a given number of samples of a single periodic waveform during a predetermined sampling rate that establishes a table resolution, repeatedly executing the following operations at the predetermined sampling rate: determining a value of a command signal frequency, setting a value to a jump factor equal to the quotient of the value of the command signal frequency divided by the table resolution, progressing the value of the phase index by the value of the jump factor, selecting a value of a commutation vector from the lookup table that corresponds to the phase index, and loading the value of the commutation vector into a corresponding PWM comparator.

A switching amplifier includes a plurality of cascade elements, each bridge circuit includes an inductive load coupled between a first leg terminal of one of the at least two leg circuits and a second leg terminal of another one of the at least two leg circuits. A first leg voltage of the first leg terminal have a phase shift relative to a second leg voltage of the second leg terminal, the phase shift is used for causing the inductive load to store electric energy and generating a minimum circulating current—I min or I min sufficient to effect conducting of a corresponding diode; each of the switches is configured to be turned on if the corresponding diode conducts current to effect zero voltage switching of the corresponding switch. The minimum circulating current—I min or I min is equal to a constant value.

An audio output circuit drives an electroacoustic conversion element. A Class D amplifier has a segmented configuration including multiple segments arranged in parallel. A pulse modulator pulse modulates an audio signal. A level detector detects the amplitude of the audio signal. A driver selectively drives the multiple segments of the Class D amplifier according to the output of the level detector.