This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.

This application describes an amplifier circuit (200) with a forward signal path with a class-D output stage (102) for generating a driving signal (Sout) based on a digital input signal (Sin). The amplifier has a first feedback path for providing a first digital feedback signal (Sfb1) based on the driving signal and a second feedback path for providing a second digital feedback signal (Sfb2) from a digital part of the forward signal path. The digital input signal (Sin) is combined with a selected feedback signal (Sfbs). The amplifier circuit is selectively operable in a first mode, in which the first feedback signal is used as the selected feedback signal, and in a second mode, in which the second feedback signal is used as the selected feedback signal. A calibration module (204) is operable to calibrate the first feedback path to reduce any DC offset when the amplifier circuit is operating in the second mode.

The invention relates to the technical field of earphone horn, more particular, relates to a horn of an integrated frequency division circuit, which includes a shell, a moving iron unit and a frequency division PCB connecting plate. The top surface of the frequency division PCB connecting plate is contacted with the bottom surface of the moving iron unit, and the side surface of the frequency division PCB connecting plate is connected with the inner edge of the bottom part of the shell; the frequency division PCB connecting plate is provided with an electronic frequency division circuit electrically connected with the moving iron unit. The horn of the integrated frequency division circuit integrates the electronic frequency division circuit, thus has the function of electronic frequency division, it reduces the production cost and the welding step, then enhances the production quality and the production efficiency.

A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

A class-D amplifier with good signal-to-noise ratio (SNR) performance is shown. The class-D amplifier includes a loop filter, a pulse-width modulation signal generator, a gate driver, a power driver, and a feedback circuit, which are configured to establish a closed amplification loop. The feedback circuit is configured to establish a feedback path. The class-D amplifier further includes a feedback breaker. The feedback breaker breaks the feedback path in response to conditions in which there no-signal information in the class-D amplifier.

Provided is a drive amplifier. A drive amplifier may include: a main circuit configured to receive an RF input signal and output a first RF output signal; and a selective bias adjustment circuit comprising a first common gate transistor to which a first common gate bias voltage is applied and a second common gate transistor to which a second common gate bias voltage is applied, and configured to output a second RF output signal using the first common gate transistor and the second common gate transistor.

Example embodiments relate to push-pull class E amplifiers. One example push-pull class E amplifier includes an input configured for receiving a signal to be amplified. The push-pull class E amplifier also includes an output configured for outputting the signal after amplification. Additionally, the push-pull class E amplifier includes a printed circuit board having a first dielectric layer and a second dielectric layer. Further, the push-pull class E amplifier includes a first amplifying unit and a second amplifying unit. Yet further, the push-pull class E amplifier includes a balun, a capacitive unit, a first line segment, a second line segment, a third line segment, and a fourth line segment. The first line segment and the second line segment are arranged on the first dielectric layer. A combined length of the third line segment and the fourth line segment corresponds to a quarter wavelength of an operational frequency of the amplifier.

A bias timing control circuit includes a current source, a bias switch circuit, a duty cycle sensing circuit, and a switching control circuit. The bias switch circuit includes a first path switch, connected between an output node of the current source and a bias amplifying circuit, and a second path switch, connected between the output node of the current source and a temperature compensation circuit. The duty cycle sensing circuit is configured to generate a timing control signal based on a duty cycle of a transmission enable signal. The switching control circuit is configured to control a first turn-on time of the first path switch during an initial startup period, and a second turn-on time of the second path switch during a normal driving period subsequent to the initial startup period to adjust a warm-up time of a power amplifying circuit based on the timing control signal.

A driver circuit is disclosed. In an embodiment a drive circuit includes a signal port with a first terminal and a second terminal, a first node and a second node, a comparator with an inverting input, a non-inverting input and an output and an operational amplifier with an inverting input, a non-inverting input and an output, wherein the first terminal is electrically conductively connected with the inverting input of the operational amplifier, wherein the second terminal is electrically conductively connected with the non-inverting input of the comparator, wherein the inverting input of the comparator is electrically conductively connected with the output of the operational amplifier, wherein the first node is electrically conductively connected with the output of the operational amplifier, wherein the inverting input of the comparator is electrically conductively connected with the inverting input of the operational amplifier, and wherein the second node is electrically conductively connected with the non-inverting input of the operational amplifier.

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.