A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

The invention relates to the technical field of earphone horn, more particular, relates to a horn of an integrated frequency division circuit, which includes a shell, a moving iron unit and a frequency division PCB connecting plate. The top surface of the frequency division PCB connecting plate is contacted with the bottom surface of the moving iron unit, and the side surface of the frequency division PCB connecting plate is connected with the inner edge of the bottom part of the shell; the frequency division PCB connecting plate is provided with an electronic frequency division circuit electrically connected with the moving iron unit. The horn of the integrated frequency division circuit integrates the electronic frequency division circuit, thus has the function of electronic frequency division, it reduces the production cost and the welding step, then enhances the production quality and the production efficiency.

In some implementations, there is provided an apparatus comprising a resonant amplifier circuit including a first inductor having a first inductive input and a first inductive output; a second inductor having a second inductive input and a second inductive output; a first switch coupled to the first inductive output; and a second switch coupled to the second inductive output, wherein the first switch and the second switched are driven out of phase, wherein the first inductor is configured to be resonant with a first capacitance associated with the first switch, and wherein the second inductor is configured to be resonant with a second capacitance associated with the second switch. Related systems and articles of manufacture are also provided.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor. The system may additionally include a modulator for generating a differential pulse-width modulation driving signal to the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch and pilot tone injection circuitry configured to inject a periodic pilot tone into the differential pulse-width modulation driving signal at a pilot tone frequency.

A power amplifying device according to an embodiment includes first to fourth BTL amplifiers and first to third switch circuits. The first to fourth BTL amplifiers outputs a first to fourth output signal. The first switch circuit is turned on or off connection between an output of the second output amplifier and an output of the third output amplifier. The second switch circuit is turned on or off connection between an output of the fifth output amplifier and an output of the eighth output amplifier. The third switch circuit is turned on or off connection between an output of the fourth output amplifier and an output of the seventh output amplifier. The first to third switch circuits are turned on when the amplitudes of the first to fourth input signals are smaller than a first threshold.