A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

A power supply for a radio-frequency power amplifier includes: first and second linear circuits, configured to linearly amplify a low-power signal and a high-power signal in a first envelope signal respectively and provide first and second voltages to the radio-frequency power amplifier respectively, wherein the low-power signal is a signal with a power ratio less than or equal to 30% in the envelope signal, and the high-power signal other than the low-power signal is a signal with a power ratio greater than or equal to 70% in the envelope signal; and a third circuit, configured to detect the linearly-amplified high-power signal and work in a constant on time control mode having a constant on time or a constant off time control mode having a constant off time so as to provide a third electric current to the radio-frequency power amplifier according to the detected linearly-amplified high-power signal.

An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.

A working state adjustment method is applied to a terminal. A power amplifier (PA) is arranged on the terminal. The method includes: determining a target channel bandwidth in which the terminal works; determining a target working state in which the PA works among optional working states according to the target channel bandwidth, in which the optional working states correspond to at least two types of working modes respectively; and adjusting the PA to work in the target working state.

An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include a phase distortion compensation circuit. The phase distortion compensation circuit may include one or more n-type metal-oxide-semiconductor capacitors configured to receive a bias voltage. The bias voltage may be set to provide the proper amount of phase distortion compensation.

A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion αVin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.

A distributed power management circuit is provided. In embodiments disclosed herein, the distributed power management circuit can achieve multiple performance enhancing objectives simultaneously. More specifically, the distributed power management circuit can be configured to switch a modulated voltage from one voltage level to another within a very short switching window, reduce in-rush current required for switching the modulated voltage, and minimize a ripple in the modulated voltage, all at same time. As a result, the distributed power management circuit can be provided in a wireless device (e.g., smartphone) to enable very fast voltage switching across a wide modulation bandwidth (e.g., 400 MHz) with reduced power consumption and voltage distortion.

Amplitude-to-phase (AM-PM) error correction in a transceiver circuit is provided. The transceiver circuit is configured to generate a radio frequency (RF) signal from a time-variant input vector for transmission in one or more transmission frequencies. In embodiments disclosed herein, the transceiver circuit is configured to determine a phase correction term from the time-variant input vector and apply the determined phase correction term to the time-variant input vector to thereby correct an AM-PM error(s) in the RF signal. By correcting the AM-PM error(s) in the transceiver circuit, it is possible to prevent undesired amplitude distortion and/or spectrum regrowth in any of the transmission frequencies, particularly when the RF signal is modulated across a wide modulation bandwidth (e.g., ≥ 200 MHz).

Phase and amplitude error correction in a transmission circuit is provided. The transmission circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from an input vector, the PMIC generates a modulated voltage, and the power amplifier circuit(s) amplifies the RF signal(s) based on the modulated voltage. When the power amplifier circuit(s) is coupled to an RF front-end circuit, unwanted amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) errors may be created across a modulation bandwidth of the transmission circuit. In this regard, in embodiments disclosed herein, the input vector is equalized based on multiple complex filters to thereby cause the AM-AM and AM-PM errors to be corrected in the transmission circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth across the modulation bandwidth of the transmission circuit.

Phase and amplitude error correction in a transmission circuit is provided. The transmission circuit includes a transceiver circuit, a power management integrated circuit (PMIC), and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from an input vector, the PMIC generates a modulated voltage, and the power amplifier circuit(s) amplifies the RF signal(s) based on the modulated voltage. In embodiments disclosed herein, the transceiver circuit is configured to equalize the input vector using multiple complex filters to thereby correct amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) errors. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth to thereby improve efficiency and linearity of the power amplifier circuit(s) across the modulation bandwidth.