Disclosed is a transimpedance amplifier. The transimpedance amplifier includes an inverter configured to have a feedback resistor and amplify a signal provided to an input side, and a common gate amplifier configured to be connected to the inverter in cascade and amplify an output of the inverter, wherein the signal provided to the input side is fed forward to a gate of the common gate amplifier through a gate resistor.

A nonlinear power supply generator is provided that nonlinearly changes a power supply voltage for a circuit during power up of the circuit to reduce high-frequency noise in an output signal from the circuit.

Certain aspects of the present disclosure provide methods and apparatus for setting a voltage level for controlling at least one of a first switch or a second switch, such that an on-resistance of the first switch matches an on-resistance of the second switch. One example circuit generally includes a third switch configured to replicate the first switch and a first cascode device connected in cascode with the third switch; a first amplifier configured to drive the first cascode device; a fourth switch configured to replicate the second switch; a second cascode device connected in cascode with the fourth switch; a second amplifier configured to drive the second cascode device; and a third amplifier configured to compare a voltage at a node coupled to the first and second cascode devices with a reference potential and to control the third switch based on the comparison to set the voltage level.

According to one embodiment, a power amplifying device includes a first amplifier configured to output a first output signal, a second amplifier configured to output a second output signal, a first circuit configured to output a third signal obtained by limiting a magnitude of a voltage value of the first output signal and a fourth signal obtained by limiting a magnitude of a voltage value of the second output signal, and a second circuit configured to transmit an average value of a voltage value of the third signal and a voltage value of the fourth signal, as a first feedback voltage to the first amplifier and the second amplifier.

Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output buffer circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals.

A power amplifier having a stack structure comprises a first driver stage that receives a power voltage from a power supply and receives and amplifies an input signal; a second driver stage that receives the power voltage from the power supply, has an input terminal connected with an output terminal of the first driver stage, and receives and amplifies an output signal from the first driver stage; and a power stage that has a power input terminal connected with a ground terminal of the first driver stage and a ground terminal of the second driver stage and receives a virtual ground voltage, and has an input terminal connected with an output terminal of the second driver stage and receives and amplifies an output signal from the second driver stage.

An operational amplifier includes an output stage, an input stage, a first auxiliary amplifier, and a second auxiliary amplifier. The output stage includes a first output transistor and a second output transistor. The input stage is configured to drive the output stage. The first auxiliary amplifier is coupled to an output of the input stage and to an input of the first output transistor. The first auxiliary amplifier is configured to bias the first output transistor for class AB operation and to isolate the input stage from a bias voltage applied to the first output transistor. The second auxiliary amplifier is coupled to the output of the input stage and to an input of the second output transistor. The second auxiliary amplifier is configured to bias the second output transistor for class AB operation, and to isolate the input stage from a bias voltage applied to the second output transistor.

A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

A source driver includes a buffer device including a plurality of buffers corresponding to a plurality of data lines, each of the plurality of buffers respectively including an amplifier configured to amplify an input signal and an output driver configured to output a driving signal to a corresponding data line among the plurality of data lines; and a switch device including a charge sharing switch configured to electrically connect the plurality of data lines to one another during a charge sharing operation, each of the amplifiers including a first current mirror having a reference current path including a first node and an output current path including a second node, and the first node of the reference current path and the second node of the output current path are electrically connected to each other during the charge sharing operation.

A circuit for inductive peaking may include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter and a switch. For example, a first node of the resistor may be connected to the output node of the driver and a second node of the resistor may be connected to the input node of the inverter. The switch may be connected between an output node of the inverter and the first node of the resistor. An input node of the driver may correspond to an input node of the circuit and the output node of the driver may correspond to an output node of the circuit.