A rail-to-rail potentiostat may require an offset current in order to support a bidirectional work electrode current at a work electrode. This offset current may improve measurements of the work electrode current made a dual-slope analog-to-digital converter, especially when the work electrode current is small, but can also lead to inaccuracies (e.g., due to a temperature coefficient) if it is not properly calibrated. Accordingly, bidirectional potentiostat is disclosed that can be configured in a normal configuration for measurement of a work electrode current or a calibration configuration for measurement (i.e., calibration) of an offset current. The reconfigurability allows calibrations to be taken as needed, on a schedule, or as specified by a user. The reconfigurability can also allow for maintaining a work electrode voltage and a work electrode current during calibration so that an electrochemical experiment using a cell coupled to the bidirectional potentiostat is unaffected by the calibration.

One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 310.sup.16 cm.sup.3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

An IC for power conversion includes bias circuitry that generates one or more bias voltages. An adaptive biasing circuit adaptively shifts an input signal having a negative value to a positive value. An operational transconductance amplifier (OTA) receives a supply bias current and the first and second bias voltages. The OTA has first and second input terminals coupled to the input signal and ground, respectively. The OTA has first and second transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively. Additional circuitry of the OTA is coupled to the second internal node. The additional circuitry insures that the voltage at the second internal node follows the voltage at the first internal node. The OTA generates an output current signal responsive to a differential input voltage applied across the first and second input terminals.

An IC for power conversion includes bias circuitry that generates one or more bias voltages. An adaptive biasing circuit adaptively shifts an input signal having a negative value to a positive value. An operational transconductance amplifier (OTA) receives a supply bias current and the first and second bias voltages. The OTA has first and second input terminals coupled to the input signal and ground, respectively. The OTA has first and second transistors coupled to the first and second input terminals through first and second resistors at first and second internal nodes, respectively. Additional circuitry of the OTA is coupled to the second internal node. The additional circuitry insures that the voltage at the second internal node follows the voltage at the first internal node. The OTA generates an output current signal responsive to a differential input voltage applied across the first and second input terminals.

An audio circuit includes N (N?1) input pins each of which receive input of a digital audio signal or an analog audio signal. When analog audio signals are input to the N input pins, an audio interface circuit applies a bias voltage to each of the N input pins via a bias resistor.

An audio circuit includes N (N?1) input pins each of which receive input of a digital audio signal or an analog audio signal. When analog audio signals are input to the N input pins, an audio interface circuit applies a bias voltage to each of the N input pins via a bias resistor.

Amplifier having electrostatic discharge and surge protection circuit. In some embodiments, a radio-frequency integrated circuit can include an amplifier, a controller configured to control operation of the amplifier, and a clamp circuit configured to provide electrostatic discharge protection and surge protection for either or both of the amplifier and the controller. The clamp circuit can include a feedback combination clamp implemented to direct a current associated with either or both of an electrostatic discharge and a surge at a first node to a second node.

Apparatuses, systems, and methods are disclosed for offset trimming for differential amplifiers. An apparatus includes a differential amplifier. A differential amplifier includes a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider. A first variable current source is coupled to a non-inverting input, so that increasing a current from the first variable current source increases a voltage at the non-inverting input. A second variable current source is coupled to an inverting input, and to an output via a voltage divider, so that increasing a current from the second variable current source decreases a voltage at the output.

A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a first output terminal. The first terminal and the control terminal of the second transistor are configured to respectively receive a first base voltage and a second control voltage. The second terminal of the second transistor and the second output module are electrically connected to a second output terminal. The feedback module is electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node of the second output module.