Patent classifications
H03F3/45076
AMPLIFIER WITH CAPABILITY OF GAIN COMPENSATION AND PIPELINED ANALOG-TO-DIGITAL CONVERTOR INCLUDING THE SAME
An amplifier includes a first differential input pair, a reset circuit, a first compensation circuit and a second compensation circuit. First differential input pair includes a first non-inverting input terminal and a first inverting input terminal, and is configured to amplify a voltage difference between first non-inverting input terminal and first inverting input terminal to generate a non-inverting output voltage and an inverting output voltage of amplifier. Reset circuit is coupled with first differential input pair, and is configured to reset non-inverting output voltage and inverting output voltage of amplifier according to a reference voltage. First compensation circuit is configured to provide a first compensation voltage to first non-inverting input terminal, and first compensation voltage is positively correlated with non-inverting output voltage. Second compensation circuit is configured to provide a second compensation voltage to first inverting input terminal, and second compensation voltage is positively correlated with inverting output voltage.
Voltage amplifier based on cascaded charge pump boosting
A method of amplifying an input voltage based on cascaded charge pump includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
Power Amplifier Self-Heating Compensation Circuit
Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain droop due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.
AMPLIFIER CIRCUIT
According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.
Low-power, high-performance regulator devices, systems, and associated methods
Low-power, high-performance voltage regulator circuit devices are disclosed and described. In one embodiment, such a device can include a first stage circuitry configured to generate a high voltage reference from a low voltage reference, a second stage circuitry coupled to the first stage circuitry, the second stage circuitry configured to receive the high voltage reference and output a voltage regulated signal, and a switch disposed between and coupled to the first stage circuitry and the second stage circuitry, the switch being configured to couple and uncouple the first stage circuitry from the second stage circuitry.
SEMICONDUCTOR INTEGRATED CIRCUIT, SENSOR READER, AND SENSOR READOUT METHOD
In a sensor reader, an IC chip has a function for amplifying and outputting a sensor signal from each sensor element included in a sensor array, and includes a plurality of channel amplifiers connected each of the sensor elements. When an output switch is closed and the IC chip is in the outputting state, channel switches operate sequentially, and sensor amplification signals are output sequentially from the channel amplifiers. When the output switch is open and the IC chip is in the non-outputting state, a bias current of an operational amplifier of the channel amplifier is decreased, the IC chip is set to a low power consumption state, and gain of the operational amplifier is decreased.
Regulator circuit for reducing output ripple
A regulator circuit includes an operational amplifier, a buffer, a power transistor, a first feedback circuit, a current sensor, and second feedback circuit. The operational amplifier drives a first node with a first voltage generated by amplifying a difference between an input voltage and a feedback voltage. The buffer drives a second node with a second voltage generated by buffering the first voltage. The power transistor has a drain receiving a supply voltage, a gate connected to the second node, and a source connected to a third node. The current sensor generates a first sensing current based on the second voltage. The second feedback circuit generates a plurality of feedback currents corresponding to a ripple of the output voltage and enhances a speed at which the ripple is reduced by providing at least one of the plurality of feedback currents to the third node.
Switched mode converter with variable common mode voltage buffer
A switching power stage for producing a load voltage at a load output of the switching power stage, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first and the second load voltages, that may include: a power converter comprising a power inductor and a plurality of switches, wherein the power converter is configured to drive a power converter output terminal; a linear amplifier configured to drive a linear amplifier output terminal; and a controller for controlling the plurality of switches and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.
REFERENCE VOLTAGES
A voltage reference circuit comprises a voltage-controlled current source; a first reference metal-oxide-semiconductor field-effect transistor having a first threshold voltage; a second reference metal-oxide-semiconductor field-effect transistor having a second threshold voltage, wherein the second threshold voltage is different to the first threshold voltage; a current mirror; and a load. The voltage-controlled current source is arranged to generate a first current proportional to a difference between the first and second threshold voltages, and the current mirror is arranged to generate a second current that is a scaled version of the first current through the load so as to produce a reference voltage.
NOISE CANCELLATION CIRCUIT
The present disclosure describes an apparatus, system, and method for cancelling noise (e.g., power supply noise). For example, the apparatus can include a load circuit, a sense resistor, and a current compensation circuit. The load circuit is configured to draw a first current (e.g., a load current). The sense resistor is configured to provide a voltage based on the first current. The current compensation circuit is configured to generate a second current (e.g., a compensation current) based on the voltage. A sum of the first current and the second current can be substantially constant.