Patent classifications
H03F3/45076
Impedance matching arrangement for an amplifier
An impedance matching arrangement for an amplifier includes first and second metallic transmission lines arranged on a ground plane, the first metallic transmission line being connected with a first power amplification stage of the amplifier, the second metallic transmission line being connected with a second power amplification stage of the amplifier; wherein the first and second metallic transmission lines are electrically coupled for transmitting an RF signal amplified by the first power amplification stage to the second power amplification stage.
Differential amplifier circuit for a capacitive acoustic transducer and corresponding capacitive acoustic transducer
An amplifier circuit, for a capacitive acoustic transducer defining a sensing capacitor that generates a sensing signal as a function of an acoustic signal, has a first input terminal and a second input terminal, which are coupled to the sensing capacitor and: a dummy capacitor, which has a capacitance corresponding to a capacitance at rest of the sensing capacitor and a first terminal connected to the first input terminal; a first buffer amplifier, which is coupled at input to the second input terminal and defines a first differential output of the circuit; a second buffer amplifier, which is coupled at input to a second terminal of the dummy capacitor and defines a second differential output of the circuit; and a feedback stage, which is coupled between the differential outputs and the first input terminal, for feeding back onto the first input terminal a feedback signal, which has an amplitude that is a function of the sensing signal and is in phase opposition with respect thereto.
Operational amplifier circuits
An implementation of an operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
AUTO-ZERO DIFFERENTIAL AMPLIFIER
An autozero amplifier may include a window comparator network to monitor an output offset of a differential amplifier. The autozero amplifier may also include an integrator to receive a signal from a latched window comparator network, and send an adjustment signal back to the differential amplifier to reduce an offset of the differential amplifier.
Two differential amplifier configuration
An apparatus is disclosed for providing a common mode voltage to the inputs of a first differential amplifier which outputs the difference between two signals. A second differential amplifier receives the output of the first differential amplifier, and the output of the second differential amplifier is fed back to the inputs of the first differential amplifier as a common mode voltage. Since both inputs of the first differential amplifier receive the fed back common mode voltage, the first differential amplifier still outputs only the difference in the two signals, but the presence of the common mode voltage allows the first differential amplifier to operate with lower noise if the voltage levels of the inputs to the first differential amplifier vary. The second differential amplifier may be of significantly lower quality and cost than the first differential amplifier, without affecting the performance of the first differential amplifier.
PROGRAMMABLE GAIN TRANSIMPEDANCE AMPLIFIER HAVING A RESISTIVE T-NETWORK FEEDBACK ARCHITECTURE AND METHOD THEREOF
A programmable transimpedance amplifiers (TIA) having T-network feedback architectures for achieving varying levels of gain based on a magnitude of an input current signal. TIA includes an operational amplifier (op-amp), a first or T-network feedback architecture that operatively connects with the op-amp at a first input terminal of the op-amp and the output terminal of the op-amp, a second feedback architecture that operatively connects with the op-amp at the first input terminal of the operational amplifier and the output terminal of the operational amplifier, an input voltage source architecture that operatively connects with a second input terminal of the operational amplifier, and at least one controller that operatively connects with each of the first feedback architecture, the second feedback architecture, and the input voltage source architecture to switch specific architectures between operative states and inoperative states to achieve a predetermined fixed output bias voltage from the operational amplifier.
POWER AMPLIFICATION DEVICE
A substrate and a chip device mounted on a main surface of the substrate are provided. The chip device is provided with a first differential amplifier including a first carrier amplifier and a second carrier amplifier, and a second differential amplifier including a first peak amplifier and a second peak amplifier. In the chip device, the first carrier amplifier and the second carrier amplifier are disposed side by side in a first direction, the first carrier amplifier and the first peak amplifier are disposed side by side in a second direction different from the first direction, the first peak amplifier and the second peak amplifier are disposed side by side in the first direction, and the second carrier amplifier and the second peak amplifier are disposed side by side in the second direction.
CURRENT SENSE AMPLIFIER
[Problem to be solved] The disclosure is to improve the temperature dependence in a current sense amplifier.
[Solution] A current sense amplifier measures a voltage drop in a drive transistor LS to measure the current flowing through the drive transistor LS. The current sense amplifier includes: a preamplifier pre-amp, to which a voltage across the drive transistor LS is inputted, and which obtains a positive output and a negative output corresponding to a voltage difference of the inputted voltage across the drive transistor; and a switch sw, which connects the input end of a common mode voltage vcm and the negative output, the common mode voltage vcm serving as the operation reference of the preamplifier pre-amp. A change of the positive output caused by turning on/off the switch sw can be detected.
Output matching network for differential power amplifier
An output matching network for a differential power amplifier comprises an output transformer having a center tap and a low pass filter. The output transformer is configured to receive a first amplified signal from a first differential output stage amplifier of the differential power amplifier and provide a first output signal to the low pass filter. The output transformer is also configured to receive a second amplified signal from a second differential output stage amplifier of the differential power amplifier and provide a second output signal to the low pass filter. The low pass filter is configured to receive the first and second output signal from the output transformer and provide a filtered output signal.
Multistage differential power amplifier having interstage power limiter
A differential power amplifier has at least an input stage and an output stage. A first output stage amplifier is configured to receive a first portion of a differential signal from the input stage at a first output stage input and provide a first amplified signal at a first output stage output. The second output stage amplifier is configured to receive a second portion of the differential signal from the input stage at a second output stage input and provide a second amplified signal at a second output stage output. Power limiter circuitry is connected to the first and/or output stage inputs and is configured to limit a power level of the differential signal prior to being received at the output stage, such that the differential power amplifier and associated filters are not damaged, while the nominal performance of the differential power amplifier at rated power is not significantly affected.