Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.

A differential power amplifier comprises an envelope tracking power supply configured to provide an envelope power supply signal to the differential power amplifier. The differential power amplifier also comprises an input stage configured to provide a differential signal having a first portion and a second portion to a differential output stage. The differential output stage comprises a first output stage amplifier configured to receive the first portion of the differential signal at a first output stage input and provide a first amplified signal at a first output stage output, as well as a second output stage amplifier configured to receive the second portion of the differential signal at a second output stage input and provide a second amplified signal at a second output stage output. The envelope power supply signal provides power for amplification.

An RF circuit for wireless devices comprises a single differential power amplifier and an impedance balancing circuit for each frequency band. The impedance balancing circuit serves both to provide an appropriate impedance at the output of the amplifier as the operating mode of the device changes, and also transforms the differential output of the amplifier to a single-ended output. The impedance balancing circuit optionally comprises a BALUN circuit and a variable capacitor that is varied as the operating mode changes in order to vary the impedance at the output of the amplifier.

An impedance matching arrangement for an amplifier includes first and second metallic transmission lines arranged on a ground plane, the first metallic transmission line being connected with a first power amplification stage of the amplifier, the second metallic transmission line being connected with a second power amplification stage of the amplifier; wherein the first and second metallic transmission lines are electrically coupled for transmitting an RF signal amplified by the first power amplification stage to the second power amplification stage.

A circuit and method for regulating an output voltage are provided. The circuit includes a fully differential first stage amplifier, a second stage amplifier, and a power output driver transistor. The first stage amplifier receives a reference voltage and feedback voltage relative to an output voltage of the power output driver transistor. A differential output of the first stage amplifier is received at differential inputs of the second stage amplifier. The second stage amplifier provides a voltage at a control terminal of the power transistor. The output voltage of the power transistor is based on the voltage at the control terminal and a supply voltage coupled to the power output driver transistor.

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

A fully differential class-D amplifier having a controlled common-mode output voltage is disclosed. The differential class-D amplifier may include a correction circuit to determine the common-mode output voltage associated with differential pulse width modulated output signals and to generate differential correction signals to control the common-mode output voltage. In some exemplary embodiments, the differential class-D amplifier may include a plurality of gain stages to generate the differential PWM output signals. The differential correction signals may be provided to at least one stage of the differential class-D amplifier.

This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

A differential current buffer circuit comprises a differential input stage supplied from a first positive and a first negative supply voltage. The input stage has a first input circuit connected between first current paths of a first current and a second mirror connected between second positive and negative supply voltages. A second input circuit is connected between first current paths of a third and a fourth current mirror connected between the second positive and negative supply voltages. The second positive voltage is higher than the first positive supply voltage, and the second negative voltage is lower than the first negative supply voltage. A first and a second output of the differential current buffer circuit are tapped off between the respective second current paths of the first and second current mirrors and the respective second current paths of the third and fourth current mirrors, respectively.

The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier.