A power amplifier includes an outphasing amplifier. The outphasing amplifier includes a first amplifier and a second amplifier, and is configured to provide a first amplified RF signal and a second amplified RF signal that is phase shifted from the first amplified RF signal. The power amplifier further includes an output circuit that is configured to combine RF power of the first and second amplified RF signals at a summing node. The output circuit includes a first branch connected between the first amplifier and a summing node and a second branch connected between the second amplifier and the summing node. The first and second branches are each configured to match an output impedance of the first and second amplifiers and to phase shift the first and second amplified RF signals for an outphasing operation using common reactive components for the match of the output impedance and the outphasing operation.

Embodiments described herein relate to a Doherty amplifier. The Doherty amplifier may include a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output. The Doherty amplifier may also include a combining network configured for combining signals emerging at outputs of the amplifiers. The signals are combined at a combining node. The combining network includes a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier. The combining network also includes a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier. The combining network also includes a first 180 degrees phase shifter and a second 180 degrees phase shifter. Additionally, the combining network includes a third impedance inverter.

A wideband power amplifier module includes a plurality of switch mode amplifiers and a plurality of impedance amplifier modules. Each switch mode amplifier includes an input to receive an input signal, and an RF output to output an RF power signal. The switch mode amplifier includes at least one semiconductor switch formed from gallium nitride (GaN). Each impedance amplifier module includes an output electrically connected to the RF output of a respective switch mode amplifier. The impedance amplifier module is configured to inject at least one impedance control signal to each RF output.

An amplifier that is configured to amplify an RF signal includes a power combiner circuit. The power combiner circuit includes a first branch connected between a first RF input port and a summing node and a second branch connected between a second RF input port and the summing node. Each of the first and second branches includes an impedance inverter. The Chireix combiner is configured to present a Chireix load modulated impedance response to the first and second RF input ports. The power combiner circuit further includes compensation elements being configured to at least partially compensate for a reactance of the Chireix combiner circuit in a Doherty amplifier mode in which a signal is applied to the first RF input port and the second RF input port is electrically open.

An apparatus includes multiple field effect transistors and multiple wires. An input wire may be configured to transfer an input signal along an axis. The field effect transistors may be configured to generate a pair of intermediate signals by amplifying the input signal. Multiple gates of the field effect transistors may be configured to receive the input signal. A topology of the gates may be rotated to be perpendicular to the axis. The field effect transistors may be located in two rows mirrored about the axis. Intermediate wires may be configured to transfer the intermediate signals parallel to the axis. A collection wire may be configured to transfer the intermediate signals toward each other and generate an output signal by combining the intermediate signals. An output wire may be configured to transfer the output signal parallel to the axis and away from the field effect transistors.

An RF amplifier utilizes first and second main amplifiers in a balanced amplifier configuration with first and second auxiliary amplifiers connected in parallel across the first and second main amplifiers, respectively. The main and the auxiliary amplifiers are biased such that the third-order nonlinearity components in the combined output current are reduced. A common or independent bias control circuit(s) control(s) the DC operating bias of the auxiliary amplifiers and establishes DC operating points on curves representing third-order nonlinear components within the drain current having a positive slope (opposite to the corresponding slope of the main amplifiers). This results in reduction of overall third-order nonlinear components in combined currents at the output. In another embodiment, a phase shift of an input to one auxiliary amplifier is used to provide a peak in minimization at a frequency associated with the phase shift.

A distributed amplifier is disclosed having a plurality of amplifier sections, each having an input gate and an output drain, and a first plurality of inductive elements coupled in series between a DA input terminal and a gate termination terminal to form a first plurality of connection nodes. Each of the connection nodes is coupled to a corresponding adjacent pair of the first plurality of inductive elements and to a corresponding input gate of the plurality of amplifier sections. A second plurality of inductive elements is coupled in series between a drain termination terminal and a DA output terminal to form a second plurality of connection nodes, each being coupled to a corresponding adjacent pair of the second plurality of inductive elements and to a corresponding output drain of the plurality of amplifier sections. An active impedance termination circuitry has a termination output coupled to the drain termination terminal.

Embodiments relate to outphasing amplifiers and amplification. One example system includes a signal splitter configured to receive an input signal and output a plurality of signals, wherein the signal splitter shifts each of the plurality of signals by a distinct phase based at least in part on a power of the input signal; a plurality of power amplifiers (PAs), each configured to amplify a distinct signal of the plurality of signals to generate a distinct amplified signal; a plurality of input matching networks, each coupled to a distinct PA of the plurality of PAs and configured to transform an input impedance of the coupled PA to an outphasing load condition based on the distinct signal the coupled PA is configured to amplify; and a combiner configured to combine the plurality of distinct amplified signals to generate an amplified input signal.

The disclosure relates to a circuit comprising a balun portion, a balanced side impedance transforming element and an unbalanced side impedance transforming element. The balun portion at least partly transforms the signal between a balanced signal input/output terminal and an unbalanced signal input/output terminal. The impedance transforming elements at least partly alter the impedance presented at the balanced and unbalanced side of the balun. In addition at least one matching transmission element is provided. By separating the role of impedance transformation from balun signal conversion, the useful bandwidth of the circuit can be improved in comparison to a balun that provides both signal conversion and impedance transformation functions.

A power amplifier cell (401) comprising: a first power amplifier (410), a second power amplifier (416) and a balun (422). The balun (422) comprising: a first transmission line (430); a second transmission line (432); a third transmission line (434); a fourth transmission line (436); and a biasing circuit (438) connected between (i) a reference terminal, and (ii) a second end of the second transmission line and a second end of the fourth transmission line.