A digital power amplifier comprising at least two individually activatable amplifiers connected to an output network comprising a first hybrid coupler. An output of a first amplifier is connected to a first input of the first hybrid coupler and an output of a second amplifier is connected to a second input of the first hybrid coupler such that activating an amplifier of the at least two amplifiers causes the amplifier to load modulate another activated amplifier of at least two amplifiers.

Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.

In some examples, a hybrid Chireix-Doherty amplifier comprises a first and second input network, a main amplifier coupled to a first output of the first input network, an auxiliary amplifier coupled to a second output of the second input network, and a combiner network. The combiner network is coupled to a first output of the main amplifier and an output of the auxiliary amplifier. The combiner network includes an output node for coupling to a load, e.g., an antenna of a base station for a radio network. The main amplifier is implemented as an inverse class-F amplifier.

According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance transmission line such as a microstrip or coplanar waveguide is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit.

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

A power amplifier circuit includes a first impedance transformer circuit arranged to connect with a carrier device, and a second impedance transformer circuit arranged to connect with a peaking device. Both the first and the second impedance transformer circuit include a parallel impedance transformer arrangement.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

A power amplifier includes an amplifier circuit group including multiple amplifier circuits, a distributing circuit that distributes an input signal to each of the multiple amplifier circuits, and a combining circuit that combines output signals from the multiple amplifier circuits. Each of the multiple amplifier circuits includes an amplifier transistor including multiple cell transistors having different sizes and bias circuits that supply bias current to the respective cell transistors.

A balanced amplifier system having input and output quadrature couplers or equivalents thereof and two amplifiers there between. An RF signal is presented to a first input of an input quadrature coupler such that an amplified RF signal is output at a first output of the output quadrature coupler. A RF control signal is presented to a second input of the quadrature coupler such that an amplified control signal is outputted at the other output of the output quadrature coupler. The system is configured to reflect the amplified signal back into the second port of the output quadrature coupler in order to vary an impedance seen by the amplifiers of the balanced amplifier.

Doherty power amplifiers (DPAs), and related circuits, devices, systems and methods of operation, are disclosed herein. In an example embodiment, a system includes a first transistor device operable as a carrier amplifier, a second transistor device operable as a peaking amplifier, and at least one first integrated passive device (IPD) coupled between a combining node and each of carrier and peaking amplifier output ports. The system includes a first frequency-corrective network coupling the carrier amplifier output port with the node, where the network is formed at least in part by the at least one first IPD and is configured to operate as a first quasi-inverter network that includes a low-pass network. Additionally, the system includes a second frequency-corrective network coupling the peaking amplifier output port with the node, where the network is formed at least in part by the at least one first IPD and includes a bandpass network.