A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

An embodiment of a distributed amplifier includes an output collection line, a plurality of tap nodes distributed along the output collection line, and a plurality of amplification paths coupled to the tap nodes. An embodiment of an amplification path includes an amplifier and a compensation circuit. The amplifier is configured to receive and amplify an input RF signal to produce an amplified RF signal at an amplifier output. A compensation circuit input is electrically coupled to the amplifier output, and a compensation circuit output is electrically coupled to one of the tap nodes. The compensation circuit includes a series inductance electrically coupled between the compensation circuit input and the compensation circuit output, and a shunt capacitance electrically coupled between the series inductance and a ground reference node. The amplifiers and the compensation circuit may be monolithically implemented on a single substrate, or may be implemented on separate substrates.

A distributed driver for an optic signal generator has a first amplifier cell with one or more amplifiers configured to receive and amplify an input signal to create a first amplified signal. A second amplifier cell has one or more amplifiers configured to receive and amplify the input signal to create a second amplified signal. A first conductive path and second conductive path connects to the first amplifier cell and the second amplifier cell such that the inductance associated with the first and second conductive path counteracts a capacitance associated with the first amplifier cell and the second amplifier cell. A variable capacitor may be part of the first amplifier cell and/or the second amplifier cell to selectively tune the capacitance of the distributed driver. A distributed bias circuit may be part of the first amplifier cell and/or the second amplifier cell to bias an optic signal transmitter.

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.

A Doherty power amplifier includes a main power amplification circuit, an auxiliary power amplification circuit, a connection circuit, and an impedance conversion circuit. An output end of the main power amplification circuit and an output end of the auxiliary power amplification circuit are connected to two ends of the connection circuit separately by using bonding wires. The output end of the auxiliary power amplification circuit is further connected to one end of the impedance conversion circuit by using a bonding wire, and the other end of the impedance conversion circuit is connected to an output load.

Provided are a harmonic control-based class-J distributed power amplifier and an optimization method thereof. The object of the present disclosure aims to solve the problems of low output power, low efficiency and low gain of distributed amplifiers resulting from non-uniform drive states of transistors at different positions and the like in the distributed amplifiers. The harmonic control-based distributed power amplifier includes an input artificial uniform transmission line, an output artificial non-uniform transmission line, and plural gain units. Two ports of the output artificial non-uniform transmission line are respectively connected with reactive terminals, and in each gain unit, a gate electrode of a transistor is connected with an RC parallel resonant circuit. In the present disclosure, based on load pull method and harmonic control technology, a purely reactive terminal network is added in the NDA terminal open-circuit structure.

In a Doherty amplifier, the number of amplifiers contributing to an amplification operation changes depending on power of an input signal, the Doherty amplifier including at least four or more amplifiers, in which order in which the amplifiers contribute to the amplification operation differs depending on a frequency of the input signal.

A distributed amplifier includes: a transmission line having an input end that an input signal is input to; a transmission line having an output end that an output signal is output from; an input termination resistor connected to an end terminal of the transmission line; a plurality of unit cells arranged along the transmission lines, and having input terminals connected to the transmission line and output terminals connected to the transmission line; and a variable current source having one end connected to the end terminal of the transmission line and another end connected to a power supply voltage, and capable of adjusting a current amount between the transmission line and the power supply voltage.

Systems, circuits, and methods for a cross-coupled differential transistor amplifier. The cross-coupled transistor amplifier can be used in a multi-section amplifier, such as a 6-section differential distributed amplifier. Each cross coupled transistor includes a first transistor and a second transistor, wherein a drain of the first transistor is connected via at least one capacitor and at least one resistor to a gate of the second transistor, and a drain of the second transistor is connected via at least one additional capacitor and at least one additional resistor to a gate of the first transistor.

An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (M.sub.CG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (M.sub.CG1) further having a first source (112) coupled to the first input (102). A second transistor (M.sub.CS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (M.sub.CS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (M.sub.CS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (M.sub.CS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (M.sub.CG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (M.sub.CG2) further having a fourth source (132) coupled to the second input (104). A first load (Z.sub.L1) is coupled between the first output (106) and a second voltage rail (136). A second load (Z.sub.L2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L.sub.1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L.sub.2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (M.sub.CG1) is substantially equal to transconductance of the fourth transistor