The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.

A driver that drives an optical device, such as laser diode (LD) and/or optical modulator, is disclosed. The driver includes a variable gain amplifier (VGA) and a post amplifier. The post amplifier amplifies an output of the VGA to a preset amplifier as varying the gain of the VGA. The VGA includes two differential pairs each amplify the input signal oppositely in phases thereof and outputs of the differential pairs are compositely provided to the post amplifier. The gain of the VGA is varied by adjusting contribution of the second differential pair to the output of the VGA.

A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a 3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

A differential amplifier includes an amplifying stage that outputs an output signal by amplifying an input signal with a gain set by a control signal, and an adjusting stage that stabilizes a DC level of the output signal. The amplifying stage includes a first source supplying a first current, and a load, and determines a ratio of a current flowing through the load to the first current depending on the input signal and the control signal, and generates the output signal from a voltage drop of the load. The adjusting stage includes a second source supplying a second current, and a monitor resistor, and generates a monitor current divided from the second current by the ratio, and duplicates the DC level as a voltage drop of the monitor resistor caused by the monitor current, and controls the first current source and the second current source depending on the DC level.

A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

A variable gain amplifier circuit includes a differential pair of transistors and a variable current source circuit. The differential pair of transistors generates an output signal based on an input signal. The variable current source circuit is coupled to the differential pair of transistors. A gain of the output signal relative to the input signal varies in response to variations in a bias current through the variable current source circuit. The variable gain amplifier circuit maintains a common mode voltage of the output signal substantially constant in response to the variations in the bias current through the variable current source circuit.

A phase shifter component is described. Inputs are arranged to selectively receive an inphase component of an in-phase (I) signal or an outphase I signal 180 out of phase with the inphase I signal, and to selectively receive an inphase component of a quadrature-phase (Q) signal or an outphase Q signal 180 out of phase with the inphase Q signal. A first gain portion includes only two transistor elements arranged to amplify the received outphase or inphase I signal. A second gain portion includes only two transistor elements arranged to amplify the received outphase or inphase Q signal. The first and second gain portions are configured to control the gain of the received outphase or inphase I signal and the received outphase or inphase Q signal, respectively, to provide a composite output signal with a desired phase shift between 0 and 360.

An amplification circuit may include an input terminal, an output terminal, a first amplification path and a second amplification path. The first amplification path may include a first transistor and a second transistor cascoded between the input terminal and the output terminal. The second amplification path may include a third transistor coupled between the input terminal and the output terminal. A control terminal of the first transistor and a control terminal of the third transistor are coupled to the input terminal. A first terminal of the second transistor may be coupled to a second terminal of the first transistor. The first amplification path and the second amplification path may be configured to operate independently of each other. A second terminal of the third transistor and a second terminal of the second transistor are coupled to a common node. In the second amplification path, the transistor closest to the common node is a common-source transistor or a common-emitter transistor.

The present invention discloses a variable gain amplifier circuit having linearity compensation mechanism is provided. A lower amplification transistor of a lower branch of an amplification circuit is controlled by an AC input signal. Upper amplification transistors of an upper branch generate an AC output signal at an amplification output terminal. An amplification control circuit controls the turn-on and turn-off of the upper amplification transistor according to an amplification control voltage. An inductor is electrically coupled between a power supply terminal and the amplification output terminal. In a gain adjustment circuit, each of adjustment control circuits controls the turn-on and turn-off of each of adjustment transistors according to a adjustment control voltage. A first voltage adjustment circuit adjusts an impedance of each of the adjustment transistors to further adjust an AC cross voltage relation between the lower amplification transistor and the upper amplification transistors.

A variable gain amplifier includes a control unit to acquire set gain information related to a setting of a gain, and, on the basis of the set gain information, output a current to a first reference current transistor and a second reference current transistor in such a manner that the sum of the value of a current to the first reference current transistor and the value of a current to the second reference current transistor becomes constant, and output, to a first variable impedance circuit and a second variable impedance circuit, a voltage obtained by multiplying the absolute value of the difference between the value of a current to the first reference current transistor and the value of a current to the second reference current transistor by a coefficient.