An apparatus includes a preamplifier stage to receive a power supply voltage and generate an output based upon an input. In particular, the preamplifier stage includes a biasing device coupled between the output and a ground node to bias a DC voltage level of the output independently of the power supply voltage. The preamplifier stage also includes a complementary circuit to receive the input and generate the output. The complementary circuit reuses a current through the preamplifier stage to provide an increased transconductance of the preamplifier stage for a given current level.

Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-g.sub.m biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).

An RF transceiver front-end circuit includes an antenna, a first transceiving switch, a reception processing unit, a transmission processing unit and a transmission unit. The reception processing unit includes a low-noise amplifier, a first variable gain amplifier at a back-end circuit of the low-noise amplifier, and a first phase shifter at a back-end circuit of the first variable gain amplifier, wherein a phase of the first variable gain amplifier is constant. The transmission processing unit includes a power amplifier, a second phase shifter at a front-end circuit of the power amplifier, and a second variable gain amplifier at a front-end circuit of the second phase shifter, wherein a phase of the second variable gain amplifier is constant. The transmission unit includes a transmission line and a plurality of passive phase adjustors controlled to change a phase shifting angle of a signal on the transmission line.

Hybrid variable gain amplifiers and methods of controlling hybrid VGAs are disclosed. The hybrid VGA includes a first portion that provides a current path between a positive input and a positive output, and a current path either between the positive input and a negative output, in a first mode of operation, or between the positive input and a voltage source, in a second mode of operation. A second portion of the VGA provides a current path between a negative input and the negative output, and a current path either between the negative input and the positive output, in the first mode of operation, or between the negative input and the voltage source, in the second mode of operation. Control voltages selectively enable the paths in the first or second mode of operation. The control voltages further control amount of current flow in the enabled paths.

Reference oscillators are ubiquitous in timing applications generally, and in modern wireless communication devices particularly. Microelectromechanical system (MEMS) resonators are of particular interest due to their small size and potential for integration with other MEMS devices and electrical circuits on the same chip. In order to support their use in high volume low cost applications it would be beneficial for MEMS designers to have MEMS resonator designs and manufacturing processes that whilst employing low cost low resolution semiconductor processing yield improved resonator performance thereby reducing the requirements of the oscillator circuitry. It would be further beneficial for the oscillator circuitry to be able to leverage the improved noise performance of differential TIAs without sacrificing power consumption.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Disclosed herein are signal amplifiers that have an input impedance that varies over different bias currents. The signal amplifier includes a gain stage with a plurality of switchable amplification branches that are each capable of being activated such that one or more of the activated amplification branches provides a targeted adjustment to the input impedance. In addition, disclosed herein are signal amplifiers that have a variable-gain stage configured to provide a plurality of gain levels that result in different input impedance values presented to a respective signal by the variable-gain stage. The variable-gain stage can include a plurality of switchable amplification branches that provide a targeted adjustment to the respective input impedance values. The variable-gain stage can include a plurality of switchable inductive elements that are configured to be activated to provide a targeted adjustment to the respective input impedance values.

Use of a closed loop APC may involve a problem of cost and power consumption due to increased circuit scale. The semiconductor device includes a power amplifier that amplifies an output from a transmission circuit and a regulator that supplies power to the power amplifier. The regulator includes an operational amplifier comprising a loop gain control circuit and a loop gain control voltage generation circuit that supplies control voltage to the loop gain control circuit. The loop gain control voltage generation circuit minimizes a loop gain of the operational amplifier when starting up the regulator.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.