This automatic gain control circuit is provided with a variable gain amplifier for amplifying a received signal, has a small circuit size, and makes it possible to reduce the effect of superimposed external noise input within the frequency bandwidth of a received signal. The automatic gain control circuit supplies the output of the variable gain amplifier to an analog/digital converter and comprises: a frequency selection circuit that is connected to the output of the analog/digital converter and that selects a signal within the frequency bandwidth of a received signal, said signal having a narrower bandwidth than the frequency bandwidth; and a control signal generation circuit that generates a control signal for the variable gain amplifier on the basis of the strength of the signal selected by the frequency selection circuit.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

An apparatus and method for controlling power in a communication system are provided. The method includes amplifying an input signal by a second processor farther from an antenna than a first processor, and determining whether to enable or disable each of the first processor and the second processor based on results from the amplification by the second processor. Another method includes amplifying an input signal from an antenna by a second processor electrically farther from the antenna than a first processor, and determining whether to operate the first processor and the second processor based on a value related to a reception state for the amplified signal by the second processor.

Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

Provided is a receiver including an oscillator (OSC) configured to generate an oscillation signal based on a radio signal, a clocked envelope detector (ED) configured to detect an envelope of the oscillation signal and hold a peak value of the envelope during a time interval, and an analog-to-digital converter (ADC) configured to convert the peak value of the envelope into a digital signal.

The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.