Patent classifications
H03G3/3052
Baseband filter for current-mode signal path
One or more systems, devices and/or methods of use provided herein relate to a baseband filter that can be used in a current-mode end-to-end signal path. The current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. In one or more embodiments, a device used in the signal path can comprise a baseband filter that receives an input current and outputs an output current. The baseband filter can comprise a feedback loop component having an active circuit branch and a passive circuit branch coupled in a loop. A mirroring device can be coupled to the feedback loop component and can provide an output of the device. Selectively activating the mirroring device can vary gain, such as of the mirroring device.
Apparatus and method for controlling gain of received signal in wireless communication system
The disclosure relates to a 5.sup.th generation (5G) or pre-5G communication system for supporting a higher data rate beyond a 4.sup.th generation (4G) communication system, such as Long Term Evolution (LTE). An operation method and a terminal are provided. The method includes acquiring information and determining an initial value for an automatic gain control (AGC) operation for a signal received from a transmission device, receiving a signal from the transmission device, and performing the AGC operation for the received signal by using the initial value determined based on the information.
ADAPTIVE WIRELESS CONFIGURATION BASED ON INPUT POWER
Disclosed herein are related to systems and methods for adaptively configuring various components of a wireless device. In one aspect, the wireless device includes a first low noise amplifier, a second low noise amplifier, and an attenuator coupled between the first low noise amplifier and the second low noise amplifier. In one aspect, the wireless device includes one or more processors configured to determine an input power level at the first low noise amplifier. In one aspect, the one or more processors are configured to determine a group of configurations of the first low noise amplifier, the attenuator, and the second low noise amplifier, according to the determined input power level at the first low noise amplifier. In one aspect, the one or more processors are configured to set the first low noise amplifier, the attenuator, and the second low noise amplifier, according to the determined group of configurations.
ANALOG RECEIVER FRONT-END WITH VARIABLE GAIN AMPLIFIER EMBEDDED IN AN EQUALIZER STRUCTURE
A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.
METHOD, DEVICE, AND STORAGE MEDIUM FOR HYBRID AUTOMATIC GAIN CONTROL IN COMMUNICATION SYSTEM
Embodiments of the present disclosure provide a method, a device, and a storage medium for hybrid automatic gain control in a communication system. The method includes amplifying an input signal to generate an amplified signal which is converted into a plurality of output signals; obtaining a moving average amplitude of a plurality of output signals of a current input signal; and calculating a signal amplitude difference according to the moving average amplitude and a desired output signal amplitude level; calculating a signal amplitude ratio according to a plurality of output signals of two previous output signal blocks and AGC gains corresponding to the plurality of output signals of the two previous output signal blocks; obtaining a step size according to the signal amplitude difference and the signal amplitude ratio; and calculating an AGC gain of the current input signal according to the step size and a corresponding previous AGC gain.
AUTOMATIC GAIN CONTROL CIRCUIT, CORRESPONDING RECEIVER, TRANSMITTER AND METHOD
A receiver or transmitter circuit includes a signal propagation path between a radio-frequency (RF) signal node and a baseband processing circuit. Variable gain circuitry is configured to vary a gain applied to a signal propagating between the RF signal node and the baseband processing circuit. The variable gain circuitry varies the gain via first, coarse steps as well as via second, fine steps. This facilitates fine matching of the gains experienced by signals propagating over the in-phase and the quadrature branches in the transmitter and/or receiver circuit.
Receiver circuits with blocker attenuating mixer
A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.
AMPLIFIER WITH INTEGRATED NOTCH FILTER
Techniques for providing low-cost and effective jammer rejection for an amplifier is disclosed. The amplifier includes an input node and an output node, a first transistor and a second transistor, a load circuitry, an inductor, and a capacitor. A first terminal of the first transistor is coupled to a ground. A second terminal of the first transistor is coupled to a first terminal of the second transistor. A second terminal of the second transistor is coupled to the output node. The load circuitry is coupled between a power supply and the second terminal of the second transistor. A first terminal of the inductor is coupled to the ground through a first switch. A first terminal of the capacitor is coupled to the first terminal of the second transistor and a second terminal of the capacitor is coupled to a second terminal of the inductor.
VARIABLE GAIN LOW NOISE AMPLIFIER AND METHOD FOR CONTROLLING GAIN OF VARIABLE GAIN LOW NOISE AMPLIFIER
A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.
Fast Automatic Gain Control Circuit
An automatic gain control circuit includes a control circuit for controlling a power detector, wherein the control circuit detects a power level change of an input signal and generates a control signal to the power detector so that the power detector can respond to the power level change of the input signal quickly.