A system to control convergence of a loop to a reference value. A device, under control of the control loop, generates an output signal. A comparator compares the output signal to a reference value. Responsive to the output signal being less than the reference value, outputting an up signal and, responsive to the output signal being greater than the reference value, outputting a down signal. A counter is configured to maintain a counter value which is incremented in response to an up signal and decremented in response to a down signal. The counter outputs a gain control value. An up/down signal tracker is configured to track a pattern of up signals and down signals and compare the tracked pattern to one or more predetermined patterns such that, responsive to the up signals and down signals matching one of the one or more predetermined patterns, the counter size is decreased.

A transimpedance amplifier is provided for converting a current between its two input terminals to a voltage over its two output terminals comprising a high-speed level shifter configured for creating a difference in input DC voltage and for being transparent for alternating voltages, an input biasing network configured for reverse biasing a photodiode connected to at least one of the input terminals and transparent for a feedback signal from the feedback network which is differentially and DC-coupled with the output terminals of the voltage amplifier and outputs of the feedback network are differentially and DC-coupled with the input biasing network of which outputs are coupled with inputs of the level shifter which is differentially and DC-coupled with input terminals of the voltage amplifier.

A switched capacitor amplifier circuit includes an operational amplifier, a first capacitor and a second capacitor each having one end connected to a negative input terminal of the operational amplifier, a first switching circuit configured to connect the other end of the first capacitor and a signal source during a first operation, a second switching circuit configured to connect the other end of the second capacitor and the output terminal of the operational amplifier so as to connect the output terminal and the negative input terminal of the operational amplifier through the second capacitor during the second operation, and an impedance converter circuit configured to convert an output impedance of the signal source into a specified impedance, the impedance converter circuit being connected between the first switching circuit and the other end of the first capacitor.

An automatic gain control circuit of a transimpedance amplifier includes a transimpedance amplifier TIA1, a transimpedance amplifier TIA2, an NMOS transistor Q1, an NMOS transistor Q2, an error amplifier U3, and a bias current source Ib. An input terminal and an output terminal of the transimpedance amplifier TIA1 are connected to a drain and a source of the NMOS transistor Q1, respectively. An input terminal and an output terminal of the transimpedance amplifier TIA2 are connected to a drain and a source of the NMOS transistor Q2, respectively. An output terminal of the bias current source Ib is connected to a positive input terminal of the error amplifier U3 and the drain of the MOS transistor Q2.

An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.

A transimpedance amplifier (TIA) circuit disclosed includes an input terminal, a first TIA circuit, a second TIA circuit, a field effect transistor (FET), and a gain control circuit. The first TIA circuit outputs a voltage signal from a first output in accordance with an input current received at a first input electrically connected to the input terminal. The second TIA circuit outputs a reference signal from a second output. The FET varies a resistance between a first current terminal and a second current terminal in accordance with a control signal applied to a control terminal. The first current terminal is electrically connected to the input terminal. The second current terminal is electrically connected to the second output of the second TIA circuit. The gain control circuit detects an amplitude of the voltage signal and generates the control signal according to a detection result of the amplitude.

Provided in the present invention is an automatic gain control method for a burst-mode transimpedance amplifier. A transistor is connected in parallel at either end of a feedback resistor of a transimpedance amplifier. A gate-source voltage of the transistor is controlled by detecting and then reversely amplifying an output voltage of the transimpedance amplifier. The present invention also provides a circuit implementing the method, obviates the need for support from any particular process, and is implementable using conventional components.

A CMOS trans-impedance amplifier includes an inverting amplifier circuit and a feedback resistor. The inverting amplifier circuit includes an input end and an output end, and the feedback resistor is coupled therebetween. The inverting amplifier circuit includes at least three sequentially-connected amplifier units, and each amplifier unit includes at least three sequentially-connected nFETs, namely an input signal receiving part nFET, an intermediate part nFET and a DC signal receiving part nFET. A common connection terminal of the input signal receiving part nFET and the intermediate part nFET is configured to output an amplified voltage signal.

A limiting amplifier circuitry according to the disclosure includes: a first differential amplifier circuitry capable of adjusting, as voltage offset, a difference between direct-current voltage components of first differential signals input thereto, the first differential amplifier circuitry amplifying the first differential signals and outputting the amplified first differential signals as second differential signals; a second differential amplifier circuitry that amplifies the second differential signals with an amplification factor depending on a difference between direct-current voltage components of the second differential signals; a signal detecting circuitry that detects an amplitude of the second differential signals, determines whether or not the amplitude is larger than a threshold, and outputs a determination result; and an offset control circuitry that controls the voltage offset by using the determination result.

A system for controlling convergence of gain to a target value for a variable gain amplifier comprising a detector module configured to determine a magnitude value of a variable gain amplifier output. Also, part of this embodiment is a comparator module configured to compare the magnitude value to a target value and responsive to the comparison, generate an up_dn signal. A digital control module is configured to receive the up_dn signal and processes the up_dn signal to generate a control vector. One or more digital to analog converters are configured to convert the control vector to an analog control signal such that the analog control signal controls the gain of the variable gain amplifier. Various methods of operation exist for this hardware configured to improve convergence time to a target gain value while controlling the rate of change of the gain.