A communication system includes a carrier generator configured to generate a first carrier signal and a demodulator configured to demodulate a modulated signal responsive to the first carrier signal. The demodulator includes a filter and a gain adjusting circuit. The filter is configured to filter a first signal. The first signal is a product of the first carrier signal and the modulated signal. The filter has a first cutoff frequency and a gain. The gain of the filter is controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter based on a voltage of the filtered first signal or a voltage of a second signal. The adjustable gain circuit is configured to generate the set of control signals.

In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and output a digitally processed signal; an analog filter to receive a digital signal via an input signal path and output a drive signal via an output signal path; and a first output pad coupled to the output signal path to output a filtered digital signal based on the drive signal.

In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and output a digitally processed signal; an analog filter to receive a digital signal via an input signal path and output a drive signal via an output signal path; and a first output pad coupled to the output signal path to output a filtered digital signal based on the drive signal.

An integrated limiter and active filter constituted of: an input node; an output node; a transistor coupled between the input node and the output node; a first control circuit coupled to the control terminal of the transistor and arranged to limit the amount of current flowing through the output node to a predetermined value which is responsive to a signal received at a first reference input; a second control circuit coupled to the control terminal of the transistor and arranged to limit the voltage appearing at the output node to a predetermined value which is responsive to a signal received at a second reference input; and a third control circuit coupled to input node and arranged to provide the second reference input, the third control circuit arranged to set the second reference input responsive to the input voltage and to a predetermined maximum allowed output voltage.

A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.

An active filtering system arranged for being connected between a first power supply line and a second power supply line of a DC bus, the bus being arranged for being connected to a DC voltage source located upstream, the system including a first capacitor arranged for being connected both to the first power supply line of the bus and to the second power supply line of the bus and to the terminals whereof a voltage is applied including an AC component, a switching assembly controlled by a processor for generating a compensation voltage, opposite to the AC component of the voltage at the terminals of the first capacitor, and including a first terminal connected to the first capacitor and a second terminal intended to be connected to the second power supply line.

A method for configuring a circuit for generating samples from a target distribution comprises: receiving a matrix representing parameters associated with the target distribution; tuning a plurality of tunable capacitance circuits in a tunable capacitance network based at least in part on respective elements of the matrix, wherein the tunable capacitance network consists essentially of interconnected wires intersecting at a plurality of nodes with selected pairs of nodes of the plurality of nodes interconnected by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits and one or more nodes of the plurality of nodes connected to a common ground by a respective tunable capacitance circuit of the plurality of tunable capacitance circuits; recording respective voltage samples from the plurality of nodes of the tunable capacitance network; and storing a linear transformation of a vector of the voltage samples based at least in part on the matrix.

The disclosure provides a quantum chip parameter determination method and device, and a filtering regulation method and device, relates to the field of quantum chips, to address the problem that a large amount of space in quantum chips are occupied in order to meet the filtering function of the quantum chips having a large number of qubits; wherein Josephson junctions are provided on the coplanar waveguide of the filter, and adjusting the critical current of the Josephson junctions and changing the equivalent inductances corresponding to the filter enables regulating the center frequency of the filter; the initial length that meets the center frequency range and bandwidth range, as well as the inductance set are selected, so that the Josephson junctions can, during regulation, cover the frequencies required by all resonant cavities, encompassing all resonant cavity frequency bands through one filter.

A switching circuit outputs a modulated signal. A low-pass filter circuit receives the modulated signal and applies low-pass filtering processing at a low-pass cut-off frequency to generate a demodulated signal to a load impedance. A replicating circuit receives the modulated signal and applies a replica of the low-pass filtering processing of the low-pass filter circuit to generate a reference signal. A signal processing circuit applies signal processing to the demodulated signal and the reference signal to generate at least one indicator signal which is indicative of a variation of the low-pass cut-off frequency.

An example apparatus includes a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode. The plurality of transistors may include first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode. The plurality of transistors may further include third and fourth transistors connected in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.