A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

A vector sum phase shifter and a vector sum phase shifting method are disclosed. The method may include: passing a first reference input excitation, after being adjusted by a first current source, through a first vector direction control circuit for vector direction determination and then to a first gate width control circuit for adjustment to generate a first output signal; passing a second reference input excitation, after being adjusted by a second current source, through a second vector direction control circuit for vector direction determination and then to a second gate width control circuit for adjustment to generate a second output signal; and vectorially summing the first output signal and the second output signal.

A vector sum phase shifter and a vector sum phase shifting method are disclosed. The method may include: passing a first reference input excitation, after being adjusted by a first current source, through a first vector direction control circuit for vector direction determination and then to a first gate width control circuit for adjustment to generate a first output signal; passing a second reference input excitation, after being adjusted by a second current source, through a second vector direction control circuit for vector direction determination and then to a second gate width control circuit for adjustment to generate a second output signal; and vectorially summing the first output signal and the second output signal.

A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos θ; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin θ; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15), to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos θ; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin θ; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15), to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.