A multi-channel digital step attenuator (DSA) architecture. One embodiment includes an array comprising N channels of B selectable attenuator cells series-connected. The overall impedance of a multi-channel DSA is a function of the parallel impedances of the N channels, and transition levels are reduced by 1/N since the transient effect of switching any one attenuator cell in or out of circuit in one channel is mitigated by all other in-circuit attenuator cells in the parallel channels. The multi-channel DSA architecture enables a great design flexibility, and allows a designer to vary one or more of at least the following design parameters: the number of attenuator cells B per channel; the number N of channels per DSA; the bit weighting of each attenuator cell per channel; the maximum attenuation per channel; and the characteristic impedance ZO.sub.n of each channel.

An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.

Digital step attenuator (DSA) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (IC) die (or chip), and provide flexibility of design for various applications. Embodiments utilize one or more architectural features and/or design techniques to achieve such characteristics, including reduced resistor and FET switch sizes, reduced series stack sizes, unidirectional input power configurations, capacitor compensation to match bandwidth characteristics, activating low-power thermometer-weighted attenuator cells only after activating higher power thermometer-weighted attenuator cells, and reducing signal transients (glitches) using a thermometer-weighted configuration of attenuator cells.

An attenuating device for a bus of a controller area network bus system based on differential voltage signals. The bus has first and second bus lines, having an attenuating circuit that provides a variable electrical resistance value between the first and second bus lines and that is operable in at least three circuit states. In a first circuit state, the first and second bus lines are connected via an attenuating resistor having a first resistance value. In a second circuit state, the first and second bus lines are connected via an attenuating resistor having a second resistance value. In a third circuit state, the first and second bus lines are connected via an attenuating resistor having a third resistance value. The first resistance value is lower than the second resistance value. The second resistance value is lower than the third resistance value.

A digital step attenuator (DSA) cell and related method are provided. The DSA cell includes a first branch comprising a first resistor connected, at a first side, to an input port and, at a second side, to an output port; a second resistor connected, at a first side, to the first resistor and, at a second side, to a first transistor and a third resistor connected, at a first side, to the first resistor and, at a second side, to a second transistor. Also included in the DSA cell is a second branch, in a parallel configuration with the first resistor, that includes a fourth resistor and a third transistor. Also included is a third branch, in a parallel configuration with the first resistor, that includes a fourth transistor. The first transistor, the second transistor, the third transistor, and the fourth transistor are configured to be operated independently.

An attenuator for attenuating a signal is disclosed. The attenuator comprises a differential input port with a positive input node and a negative input node to receive the signal; and a differential output port with a positive output node and a negative output node to output the attenuated signal. The attenuator further comprises a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. Further a pair of compensation paths is connected to the first and second switched resistor networks for cancellation their parasitic leakages, where a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. The attenuator further comprises a control circuit to generate control signals for controlling the first and second switched resistor networks.

An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.

Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.

A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.