A delay line device is provided for a high frequency sampler for high frequency signal transmission, or for an oscilloscope for measuring high frequency signals. The delay line device includes two distributed tapped transmission delay lines. Each of the delay lines includes two terminals. An analog input signal is applied to a first terminal of the first delay line, and a clock signal is applied to a first terminal of the second delay line. The delay lines are configured such that the analog input signal propagates through the first delay line in an opposite direction as compared to the propagation of the clock signal through the second delay line.

A delay circuit is provided. The delay circuit includes a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay circuit. Furthermore, the delay circuit is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge an input signal being actively delayed by the delay circuit when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal. The device includes a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal. The device includes a first load connected to a drain of the third transistor. The device includes a second load connected to a drain of the fourth transistor. The device includes at least one capacitor connected in parallel between the first load and the second load.

A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

Systems and methods for a variable delay line using variable capacitors in a time delay filter are provided. In at least one embodiment, a delay line is configured to apply an adjustable time delay to an electromagnetic signal travelling through the delay line. The delay line comprises a filter that includes a first variable capacitor. Further, a capacitance of the first variable capacitor is configured to adjust the delay applied to the electromagnetic signal travelling through the delay line when varied.

An analog delay cell is provided that includes a transconductance-capacitance stage and an inductive transimpedance amplifier stage that provides an all-pass transfer function. In another embodiment, an adaptive analog delay cell including a transconductance (gm) plus capacitance (C) stage and an inductive-capacitance transimpedance amplifier (TIA) stage with digitally programmable phase-shift is provided. The adaptive analog delay cell increases the phase-shift by incorporating an LC network in the feedback path of the transimpedance stage. The disclosed analog delay cells can be used to provide delays in a tapped delay line. Also, the disclosed analog delay cells may be used to perform the multiplier and summation functions of a tapped delay line in addition to providing the delays. In another embodiment, the transimpedance amplifier stage includes an inductive-capacitive transimpedance amplifier stage.

Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.

Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

An electronically variable analog delay line including at least one segment with an electronically variable inductance. The at least one segment includes a signal path, a ground return path, and a plurality of switches configured to vary the inductance of the segment.