An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.

Data transfer rates input to and output from electronic devices are a function of I/O pad circuit structure. The load capacitance of an I/O pad may reduce the bandwidth of an I/O circuit. A reduced pad capacitance circuit may be used to reduce or eliminate the positive and physical pad capacitance associated with a capacitive pad. This negative capacitance reduces or minimizes poor signal quality arising from large pad capacitance. This improved signal may be fed into a comparator, where the signal may be improved further using an equalizer. The use of negative capacitance circuit will increase the transmit and receive signaling quality of I/O interfaces.

A compensation circuit reduces the negative effects of antenna-to-antenna coupling between proximately located antennas. The compensation circuit is coupled between first and second antenna ports. A first transmit/receive path extends from radio frequency (RF) circuitry to the first antenna port. A second transmit/receive path extends from the RF circuitry to the second antenna port. Antennas are coupled to each of the antenna ports. The compensation circuit includes negatively coupled first and second inductors, which are coupled in series between the first antenna port and the second antenna port. At least one shunt acoustic resonator is coupled between a fixed voltage node and a common node between the first and second inductors. In operation, the compensation circuit presents a negative capacitance between the first antenna port and the second antenna port over the first frequency range to reduce the effects of the antenna-antenna coupling.

A compensation circuit reduces the negative effects of antenna-to-antenna coupling between proximately located antennas. The compensation circuit is coupled between first and second antenna ports. A first transmit/receive path extends from radio frequency (RF) circuitry to the first antenna port. A second transmit/receive path extends from the RF circuitry to the second antenna port. Antennas are coupled to each of the antenna ports. The compensation circuit includes negatively coupled first and second inductors, which are coupled in series between the first antenna port and the second antenna port. At least one shunt acoustic resonator is coupled between a fixed voltage node and a common node between the first and second inductors. In operation, the compensation circuit presents a negative capacitance between the first antenna port and the second antenna port over the first frequency range to reduce the effects of the antenna-antenna coupling.

In examples, systems and methods for increasing the performance of electrically-small antennas are described. An example system comprises an electrically-small antenna having an antenna feed. The electrically-small antenna is configured to receive a signal. The system also comprises a non-foster circuit having a negative capacitance coupled to the antenna feed in a shunt position. The non-foster circuit is configured to resonate the electrically-small antenna and provide a voltage increase to the received signal. The system also comprises a buffer circuit configured to provide an impedance conversion of the voltage-increased received signal between the antenna feed and an output of the buffer circuit. The buffer circuit includes a field-effect transistor.

In examples, systems and methods for increasing the performance of electrically-small antennas are described. An example system comprises an electrically-small antenna having an antenna feed. The electrically-small antenna is configured to receive a signal. The system also comprises a non-foster circuit having a negative capacitance coupled to the antenna feed in a shunt position. The non-foster circuit is configured to resonate the electrically-small antenna and provide a voltage increase to the received signal. The system also comprises a buffer circuit configured to provide an impedance conversion of the voltage-increased received signal between the antenna feed and an output of the buffer circuit. The buffer circuit includes a field-effect transistor.

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.