There is provided a plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing container accommodating the substrate; an electrode to which a high-frequency power for generating plasma in the processing container is applied; a high-frequency power supply configured to apply the high-frequency power to the electrode; and a high-frequency power supply circuit configured to supply the high-frequency power from the high-frequency power supply to the electrode. The high-frequency power supply circuit comprises: a power supply path configured to supply a power from the high-frequency power supply to the electrode; and a matching device configured to match a high-frequency power supply-side impedance with a plasma-side impedance, the matching device comprising a negative impedance portion that is connected to the power supply path and realizes a negative impedance corresponding to a plasma-side impedance.

There is provided a plasma processing apparatus for performing plasma processing on a substrate, comprising: a processing container accommodating the substrate; an electrode to which a high-frequency power for generating plasma in the processing container is applied; a high-frequency power supply configured to apply the high-frequency power to the electrode; and a high-frequency power supply circuit configured to supply the high-frequency power from the high-frequency power supply to the electrode. The high-frequency power supply circuit comprises: a power supply path configured to supply a power from the high-frequency power supply to the electrode; and a matching device configured to match a high-frequency power supply-side impedance with a plasma-side impedance, the matching device comprising a negative impedance portion that is connected to the power supply path and realizes a negative impedance corresponding to a plasma-side impedance.

A resonator circuit, a filter with improved tunability, and a duplexer with improved tunability are disclosed. In an embodiment, the resonator circuit includes a resonator, a Z transformer and an impedance circuit, wherein the impedance circuit has an impedance Z and includes an impedance element, wherein the Z transformer is interconnected between the resonator and the impedance circuit, and wherein the Z transformer transforms the impedance Z to a new impedance ZZ and comprises a transformation circuit selected from: a generalized impedance converter (GIC), an negative impedance converter (NIC), a generalized impedance inverter (GII) and an negative impedance inverter (NII).

A resonator circuit, a filter with improved tunability, and a duplexer with improved tunability are disclosed. In an embodiment, the resonator circuit includes a resonator, a Z transformer and an impedance circuit, wherein the impedance circuit has an impedance Z and includes an impedance element, wherein the Z transformer is interconnected between the resonator and the impedance circuit, and wherein the Z transformer transforms the impedance Z to a new impedance ZZ and comprises a transformation circuit selected from: a generalized impedance converter (GIC), an negative impedance converter (NIC), a generalized impedance inverter (GII) and an negative impedance inverter (NII).

An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

In examples, systems and methods for increasing the performance of electrically-small antennas are described. An example system comprises an electrically-small antenna having an antenna feed. The electrically-small antenna is configured to receive a signal. The system also comprises a non-foster circuit having a negative capacitance coupled to the antenna feed in a shunt position. The non-foster circuit is configured to resonate the electrically-small antenna and provide a voltage increase to the received signal. The system also comprises a buffer circuit configured to provide an impedance conversion of the voltage-increased received signal between the antenna feed and an output of the buffer circuit. The buffer circuit includes a field-effect transistor.

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.

There is disclosed a negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load. The negative impedance converter comprises first and second transistors connected in a cross-over configuration. Each transistor has a source or emitter, a drain or collector and a gate or base, and each transistor further has a first biasing circuit connected to its gate or base. The first biasing circuit comprises a first DC biasing signal source and a first diode or a third transistor connected between the first DC biasing signal source and the gate or base. There is also disclosed a negative impedance converter for a matching circuit for matching an impedance of an antenna to an impedance of an RF source or load. The negative impedance converter comprises first and second transistors connected in a cross-over configuration, each transistor having a source or emitter, a drain or collector and a gate or base. The source or emitter of one transistor is configured as an RF input port and the source or emitter of the other transistor is configured as an RF output port. The drain or collector of the first transistor is connected to the gate or base of the second transistor and the drain or collector of the second transistor is connected to the gate or base of the first transistor. An impedance is connected between the drain or collector of the first transistor and the drain or collector of the second transistor. The negative impedance converter is further provided with a passive impedance adjustment network connected between the source or emitter of the first transistor and the source or emitter of the second transistor.