A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

A dynamic capacitor circuit having a first passive capacitor, a second passive capacitor, a first terminal of the first passive capacitor and a first terminal of the second passive capacitor connected together to receive an input signal through a resistor. The input signal includes a noise signal component. An alternating current (AC) coupled inverting amplifier has an input connecting a second terminal of the second passive capacitor, the second capacitor coupling the input signal to the AC coupled inverting amplifier input. A conductive path couples an output of the AC coupled inverting amplifier to a second terminal of the first passive capacitor to balance out any noise signal component of the input AC signal at the connection. The dynamic capacitor achieves an amount of noise reduction in a reduced space without applying deep trench capacitors (DTCAP) where the DTCAP is a capacitance formed in a plane perpendicular to the substrate.

A capacitor circuit includes a first terminal, a first to a third transistor and a first capacitor. The first transistor includes a first terminal configured to be coupled to a first current source and the first terminal of the capacitor circuit, and a second terminal coupled to a reference voltage terminal. The second transistor includes a first terminal configured to be coupled to a second current source, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the first terminal of the second transistor and a control terminal of the first transistor. The third transistor includes a first terminal configured to be coupled to a third current source and the first terminal of the first transistor, a second terminal coupled to the reference voltage terminal, and a control terminal coupled to the control terminal of the second transistor. The first capacitor includes a first terminal coupled to the first terminal of the capacitor circuit, and a second terminal coupled to the control terminal of the first transistor.

A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

A super scale switched capacitor for an integrated circuit is disclosed. In one embodiment the super scale switched capacitor circuit includes a capacitor coupled between a first node and a second node. A circuit is also included that contains a first circuit and a second circuit. The first circuit is configured to output a first current, which is a multiple of current effectively flowing through the capacitor from the second node to the first node. The second circuit is configured to input a second current, which is a multiple of current effectively flowing through the capacitor from the first node to the second node.

A small capacitance compensation network circuit, the first switch module (201) and the second switch (202) module are alternately switched between a switched-off state and a switched-on state, so that the compensation capacitor C3 is charged by the capacitor C1; and the third switch module (203) and the fourth switch module (204) are alternately switched between the switched-off state and the switched-on state, so that the compensation capacitor C3 is discharged to charge the capacitor C2, by controlling the alternate switch-on of the first switch module (201) and the second switch module (202), the third switch module (203) and the fourth switch module (204) causes the deviation of the capacitor C1 and the capacitor C2 to be processed and obtain the error signal. Therefore, the compensation capacitor C3 can be designed to be very small, which facilitates the integration of the integrated circuit, eliminates the need for external compensation capacitors and integrated circuit pins, reduces the system cost, and improves the reliability. Therefore, it is solved the problem that the existing compensation network technology has high cost in the power control circuit and poor reliability in the power supply.

A small capacitance compensation network circuit, the first switch module (201) and the second switch (202) module are alternately switched between a switched-off state and a switched-on state, so that the compensation capacitor C3 is charged by the capacitor C1; and the third switch module (203) and the fourth switch module (204) are alternately switched between the switched-off state and the switched-on state, so that the compensation capacitor C3 is discharged to charge the capacitor C2, by controlling the alternate switch-on of the first switch module (201) and the second switch module (202), the third switch module (203) and the fourth switch module (204) causes the deviation of the capacitor C1 and the capacitor C2 to be processed and obtain the error signal. Therefore, the compensation capacitor C3 can be designed to be very small, which facilitates the integration of the integrated circuit, eliminates the need for external compensation capacitors and integrated circuit pins, reduces the system cost, and improves the reliability. Therefore, it is solved the problem that the existing compensation network technology has high cost in the power control circuit and poor reliability in the power supply.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0 . The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.

The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.