A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell.

A method for adapting an antenna circuit including at least one first capacitive element and an inductive element in series, and at least one second capacitive element having a first electrode connected between the first capacitive element and the inductive element, wherein data representative of the voltage of said first electrode are applied to the second electrode of the second capacitive element.

The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.

A tunable impedance simulator and impedance multiplier circuit and a system for configuring a second generation voltage-mode conveyor circuit (VCII) as the tunable impedance simulator and impedance multiplier are described. The tunable impedance simulator and impedance multiplier circuit includes one VCII having a positive input terminal connected to a voltage source, a negative input terminal connected to the voltage source, and an impedance terminal Z.sub.0. The impedance terminal Z.sub.0 can be either positive or negative. When the impedance terminal Z.sub.0 is positive, a positive active inductor, a positive capacitance multiplier, and a positive resistance multiplier may be implemented. When the impedance terminal Z.sub.0 is negative, a negative active inductor, a negative capacitance simulator, and a negative resistance simulator may be implemented.

A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell.

A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

The compact C-multiplier includes four MOSFETs operating in the subthreshold region using the translinear principle. The multiplier is controllable to meet designer requirements. A Tanner Tspice simulator is used to confirm the functionality of the design in 0.13 pm CMOS Technology. The circuit operates from a 0.75 supply voltage. Simulation results indicate that the multiplication factor is large compared to existing designs.

An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.