A filtering device (20) includes an acquirer (21) and a filtering unit (22). The acquirer (21) acquires an input value that is repeatedly input. The filtering unit (22) obtains an output value by filtering for reduction of noise included in the input value. When a difference between the current input value and the past output value exceeds a first threshold, the filtering unit (22) obtains a new output value by weighting the current input value with a weight greater than a weight for obtaining the past output value.

There is provided a 2-stage moving average filter for a navigation device including a delta regulator and an N-taps average circuit. The delta regulator is used as a first stage to receive motion delta at a varied frequency, and combine or split the received motion delta to output a regulated motion delta at a fixed frequency. The N-taps average circuit receives and averages N regulated motion delta and outputs the averaged motion delta at a fixed frequency.

There is provided a 2-stage moving average filter for a navigation device including a delta regulator and an N-taps average circuit. The delta regulator is used as a first stage to receive motion delta at a varied frequency, and combine or split the received motion delta to output a regulated motion delta at a fixed frequency. The N-taps average circuit receives and averages N regulated motion delta and outputs the averaged motion delta at a fixed frequency.

An adaptive identification system, for identifying a propagation system characteristic by an adaptive filter, includes a signal generator that generates an identification input signal including a frequency component of an integer multiple of a fundamental frequency and having a periodicity satisfying a PE condition, a setting unit that sets moving average time to a fundamental period of the identification input signal, and an adaptive algorithm execution unit that uses a moving average value and a diagonal matrix to update a coefficient of the adaptive filter, the moving average value being obtained by calculating a moving average of a cross-correlation vector of a vector of the identification input signal and an observation signal with the moving average time, and the diagonal matrix being obtained by diagonalizing a matrix obtained by calculating a moving average of an autocorrelation matrix of the vector of the identification input signal with the moving average time.

A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.

Data output from each of the n delay elements and a remainder value output from a divider in the previous calculation are input to an adder, and an addition process for obtaining a total sum thereof is executed. In addition, a division process is performed by dividing the total sum output from the adder by n, and a quotient and a remainder are output from the divider. The remainder is delayed by a remainder delay element by one clock, is output to the adder, and is added in the next calculation.

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate f.sub.S for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f.sub.samp, the first clock rate f.sub.S being N times greater than the second clock rate f.sub.samp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate f.sub.samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.

A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.