A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

The invention relates to a method (100) for switching between desired value filters (26, 28) of a drive means (52) for a machine axis (10, 12) during operation. An input signal (20) is applied to the first and to the second desired value filter (26, 28) for producing a first and a second output signal (23, 33). Then any deviation between the first and the second output signal (23, 33) is determined. If the deviation falls below a threshold value, the first desired value filter (26) is separated from the drive means (52) and substantially simultaneously the second desired value filter (28) is connected to the drive means (52). The desired value filters (26, 28) have different running times (19).

A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

A digital filter setting device, a control method of the digital filter setting device, and a recording medium are provided. Filter characteristics of a digital filter after parameter setting are easily recognized by a user. A digital filter setting device (1) includes: a parameter setting part (11) receiving input of filter parameters; a step response time calculation part (14) calculating a step response time of the digital filter in a case that the filter parameters are set; and a graph generating part (12) displaying the calculated step response time in the form of graph.

A navigation device including a digital filter configured to smooth tracking is provided. The digital filter is configured to sequentially receive input data and output a tap sum, and calculate a quotient and a remainder by dividing an accumulation value with an average number, wherein the remainder is feedback to the tap sum for updating the accumulation value and the quotient is configured as output data.

Differing from the fact that the amount of register units and adder units arranged in conventional moving average filter must be increased for processing more number of reference input signals, the present invention particularly discloses a moving average low-pass filtering device. The moving average low-pass filtering device comprises a register unit and a filtering and processing unit, and is able to use identical circuit architecture to successfully treat reference input signals with a filtering process even if the number of the reference input signals is alternatively increased. Moreover, after finishing a verification experiment by a simulator, simulation results have proved that, this novel moving average low-pass filtering device still can use identical circuit architecture to complete the filtering process under nearly the same calculation efficiency even though the number of the reference input signals is alternatively increased.

A method for averaging pulsating measurement quantities is disclosed. First, time-discrete measurement values (1) of the measurement quantity are recorded. Subsequently, first filtering of the measurement values (1) is carried out with a first filter time constant, during which a first signal (2) is obtained, and second filtering of the measurement values (1) with a second filter time constant, during which a second signal (3) is obtained, the second filter time constant being greater than the first filter time constant. Intersection points (4), at which the first signal (2) and the second signal (3) intersect, are then determined. Lastly, the arithmetic mean of the measurement values (1) between the intersection points (4) is taken.

A frequency synthesizer includes a hardware digital controlled oscillator (HDCO) running at a first clock rate f.sub.S for generating an output clock signal in response to a control input, and a digital phase locked loop (DPLL) responsive to a reference input sampled at a second clock rate f.sub.samp, the first clock rate f.sub.S being N times greater than the second clock rate f.sub.samp, The DPLL includes a loop filter and a software digital controlled oscillator (SDCO). A first, first order linear interpolation anti-imaging filter running at a clock rate higher than said second clock rate f.sub.samp is coupled to an output of the loop filter for providing the control input to the HDCO. A second, first order linear interpolation anti-imaging filter running at said second clock rate coupled to the output of said loop filter to provide an input to said SDCO.

Differing from the fact that the amount of register units and adder units arranged in conventional moving average filter must be increased for processing more number of reference input signals, the present invention particularly discloses a moving average low-pass filtering device. The moving average low-pass filtering device comprises a register unit and a filtering and processing unit, and is able to use identical circuit architecture to successfully treat reference input signals with a filtering process even if the number of the reference input signals is alternatively increased. Moreover, after finishing a verification experiment by a simulator, simulation results have proved that, this novel moving average low-pass filtering device still can use identical circuit architecture to complete the filtering process under nearly the same calculation efficiency even though the number of the reference input signals is alternatively increased.

A fixed latency configurable tap or fixed-tap digital filter may filter a signal in a fixed amount of time, regardless of the number of taps. The filter may include one or more of a clock, a plurality of registers in a shift register, an adder, an accumulator, and/or a scaler. In at least one embodiment, a running average may be maintained as samples are received such that the latency remains fixed with a constant number of clock cycles.