A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.

Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

A circuit device includes a digital signal processor (DSP) that performs first up-sampling processing of up-sampling up-sampling target data having a first sampling frequency from the first sampling frequency to a second sampling frequency by first interpolation processing, and an arithmetic circuit that performs second up-sampling processing of up-sampling data output from the DSP from the second sampling frequency to a third sampling frequency by second interpolation processing.

Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

A method is provided for resampling an audio-frequency signal in an audio-frequency signal encoding or decoding operation. The resampling is carried out by a method of interpolation of an order greater than one. The method is such that the interpolated samples are obtained by calculating a weighted average of possible interpolation values calculated over a plurality of intervals covering the time location of the sample to be interpolated. A resampling device is provided, which implements the method, and also an encoder and decoder including at least one resampling device.

This application relates to an optimization for a technique for filtering an input signal according to a convolution kernel that is stored in a floating point format. A method for filtering the input signal includes: receiving a set of filter coefficients that define the convolution kernel; determining an order for a plurality of floating point operations configured to generate an element of an output signal; and filtering the input signal by the convolution kernel to generate the output signal. Each floating point operation corresponds with a particular filter coefficient, and the order for the plurality of floating point operations is determined based on a magnitude of the particular filter coefficient associated with each floating point operation. The filtering is performed by executing the plurality of floating point operations according to the order. The data path can be a half-precision floating point data path implemented on a processor.

Provided, among other things, is an apparatus that converts a signal from one sampling domain to another, and which includes: an input line for accepting an input signal and a processing branch. The processing branch includes a branch input coupled to the input line for inputting data samples that are discrete in time and in value, a quadrature downconverter, a first and second lowpass filter, a first and second polynomial interpolator, and a rotation matrix multiplier that provides a phase rotation. The processing branch generates data samples at a sampling interval that differs from the sampling interval associated with the signal provided to the branch input, e.g., with the difference in the sampling intervals depending on fluctuations in the output period of a local oscillator. Certain embodiments include multiple such processing branches, e.g., operating on different frequency bands of the input signal.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

A circuit device includes a digital signal processor (DSP) that performs first up-sampling processing of up-sampling up-sampling target data having a first sampling frequency from the first sampling frequency to a second sampling frequency by first interpolation processing, and an arithmetic circuit that performs second up-sampling processing of up-sampling data output from the DSP from the second sampling frequency to a third sampling frequency by second interpolation processing.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.