A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.

The disclosed multi-level driving data transmission circuit and operating method include: a first driving module including a first signal generating unit and a first three-state driver, and a second driving module, including a second three-state driver. The first input terminal of the second three-state driver is coupled to the output terminal of the first three-state driver. The first signal generating unit includes a first and second input terminals, and an output terminal. The output terminal of the first signal generating unit couples to the second input terminal of the first three-state driver. The first signal generating unit receives the first signal through its first input terminal and the first feedback signal of the first signal from the second driving module through its second input terminal. The resultant first control signal has an effective signal width wider than the first signal. The first control signal inputs to the first three-state driver.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

A display panel includes sub-pixels each including a light-emitting element and a pixel circuit including a first transistor and a second transistor; a timing control unit to generate bias data based on first characteristic information of the first transistor, and generate correction data based on second characteristic information of the second transistor; and a data sensing driving unit configured to receive the bias data and the correction data, and output a bias voltage and a grayscale voltage to the pixel circuit. The pixel circuit includes the first transistor to output a driving current to the light-emitting element; a first driving circuit to control a magnitude of the driving current based on the bias voltage; and a second driving circuit including the second transistor and configured to control a pulse width of the driving current based on the grayscale voltage.

A sensing circuit includes: a comparison circuit for comparing an input signal to a corresponding limit threshold; and a control circuit for periodically selecting the limit threshold and sampling a comparison result to execute an interval determination step, thus determining an interval of the input signal. The interval determination step includes steps S100 and S200. Step S100: when the input signal is higher than an ascending upper limit threshold for consecutive plural times, assigning a higher adjacent interval as a following interval; when the input signal is lower than a descending lower limit threshold for consecutive plural times, assigning a lower adjacent interval as a following interval; and executing the interval determination step corresponding to the following interval. Step S200: When no adjacent interval is assigned as the following interval, generating an interval output signal corresponding to the interval and entering the corresponding step S100.

Control circuitry for controlling a current through an inductor of a power converter, the control circuitry comprising: comparison circuitry configured to compare a measurement signal, indicative of a current through the inductor during a charging phase of the power converter, to a signal indicative of a target average current through the inductor for the charging phase and to output a comparison signal based on said comparison; detection circuitry configured to detect, based on the comparison signal, a crossing time indicative of a time at which the current through the inductor during the charging phase is equal to the target average current for the charging phase; and current control circuitry configured to control a current through the inductor during a subsequent charging phase based on the crossing time.