A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

One example includes an Ising machine system. The system includes a plurality of ring oscillators that are each configured to propagate an oscillation signal. Each of the ring oscillators can be cross-coupled with at least one other of the ring oscillators via a respective one of the oscillation signals to provide a respective phase coupling between the respective cross-coupled ring oscillators. The system also includes an Ising machine controller configured to generate control signals corresponding to parameters of an Ising problem and including a plurality of delay selection signals. The Ising machine controller can provide at least one of the delay selection signals to each of the ring oscillators. The delay selection signal can be configured to set a variable propagation delay of the ring oscillator to control the relative phase coupling of each of the ring oscillators to each of the at least one other of the ring oscillators.

Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.

A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.

The present invention discloses a power supply stabilizing circuit having noise suppressing mechanism configured to drive a voltage-control oscillating circuit that includes a current-adjusting N-type transistor including a drain, a source and a gate and an adjusting voltage generation circuit. The drain receives a first operation voltage. The source generates a power signal to the voltage control oscillator circuit. The gate receives an adjusting voltage. The adjusting voltage generation circuit operates according to a second operation voltage higher than the first operation voltage and receives a reference voltage that is a division of the first operation voltage to generate the adjusting voltage. The adjusting voltage is a sum of the reference voltage and a threshold voltage of the current-adjusting N-type transistor such that the current-adjusting N-type transistor operates in a saturation region to keep a current variation amount of the power signal smaller than a predetermined value.

The present disclosure is to provide a voltage control device that is capable of lowering power consumption by bringing the power supply voltage of a controlled circuit as close to the lowest operating voltage as possible while maintaining the power supply voltage equal to or higher than the lowest operating voltage.

A voltage control device according to the present disclosure includes: a power supply circuit that supplies electric power to an input terminal of a controlled circuit; a power supply voltage control circuit that controls the power supply voltage to be supplied from the power supply circuit to the controlled circuit, on the basis of the clock signal to be supplied to the controlled circuit; and a clock generation circuit that receives a power supply that is the internal voltage to be applied to a second internal circuit region at a second wiring distance from the input unit, and generates the clock signal on the basis of the internal voltage, the second wiring distance being longer than a first wiring distance at which a first internal circuit region is located in the controlled circuit, the first wiring distance and the second wiring distance being wiring distances in the controlled circuit from the input unit.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

A true random number generator circuit includes a ring oscillator and a plurality of sampling circuits. The ring oscillator includes a plurality of series-connected stages coupled together in a ring. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. A sampling circuit of the plurality of sampling circuits has an input coupled to a node located between two adjacent stages of the plurality of series-connected stages. Every node of the ring oscillator is coupled to a corresponding sampling circuit of the plurality of sampling circuits. In another embodiment, a method for generating a random number is provided.

Methods and devices for determining integrated circuit (IC) device degradation over time are provided. Transistors are the basic building blocks of IC devices. The degradation of the transistors in IC devices over time leads slowly to decreased switching speeds. To monitor the condition of an IC device as it ages, oscillator circuitry operating at switching frequencies of various circuits in the IC device may be included and monitored for changes in switching frequency over time. A degraded condition of the IC device may be determined when the change in switching frequency exceeds a threshold value.