An integrated circuit includes a first portion of a stacked ring oscillator coupled between a first supply voltage node and a common node, wherein the first supply voltage node provides a local supply voltage for the first portion and the common node provides a local ground for the first portion. The integrated circuit includes a second portion of the stacked ring oscillator coupled between the common node and a second supply voltage node wherein the common node provides a local supply voltage for the second portion and the second supply voltage node provides a local ground for the second portion. The integrated circuit also includes a voltage divider having a first resistive element coupled between the first supply node and the common node and a second resistive element coupled between the common node and the second supply node.

A voltage controlled oscillator (VCO) and a method of operating the VCO are disclosed. The VCO includes an inductor device, a capacitor device coupled in parallel with the inductor device through first and second nodes, and a pair of cross-coupled transistors coupled in parallel with the inductor device and the capacitor device through the first and second nodes. At least one of the pair of cross-coupled transistor includes a plurality of sub transistors coupled in parallel. The sub transistors are individually switchable to adjust current drive capability of each of the sub transistors. Each of the sub transistors includes a first gate and a second gate.

An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.

Provided are a temperature sensor, an array substrate, and a display device. In the temperature sensor, a low-pass filter is disposed between a ring oscillator and a comparator, so that a square-wave signal output from the ring oscillator passes through the low-pass filter and a high-frequency component in the square-wave signal output from the ring oscillator is directly filtered out by the low-pass filter, thereby improving a signal-to-noise ratio of the ring oscillator and a test accuracy of the temperature sensor.

An object of the present invention is to provide a semiconductor device including an oscillator circuit including a circuit between inverters. In the circuit, a sum of the length (a.sub.1) of a wiring path between a terminal A and a terminal C.sub.1 and a length (b.sub.1) of a wiring path between a terminal D.sub.1 and a terminal B is substantially equal to a sum of the length (a.sub.2) of a wiring path between the terminal A and a terminal C.sub.2 and the length (b.sub.2) of a wiring path between a terminal D.sub.2 and the terminal B.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

A tunable delay circuit includes a first multiplexer, a delay chain, and a second multiplexer. The first multiplexer selects an input signal or a feedback signal as a first output signal according to an enable signal. The delay chain delays the first output signal for different time periods so as to generate a plurality of delay signals. One of the delay signals is used as the feedback signal. The second multiplexer selects one of the delay signals as a second output signal according to a pass signal.