Methods of triggering a test and measurement instrument having a plurality of inputs include the step of generating a trigger signal in response to every occurrence of any one of a plurality of specified trigger events. A first specified trigger event occurs in at least a first one of the inputs and a second specified trigger event occurs in at least a second one of the plurality of inputs. A specified trigger event may include at least one selected input from the plurality of inputs and a selected activity type. Some methods include configuring each of a plurality of event activity detectors to produce a pulse in a logic signal in response to every occurrence of one of the specified trigger events. The plurality of logic signals are combined in a logical OR circuit to generate the trigger signal. Trigger circuits configured according to these methods are also disclosed.

A load abnormality detecting circuit for an inverter to detect abnormality of a load during an operation of the inverter which has a switching element and a phase synchronizing loop controlling an output frequency to be a resonance frequency of the load, the load abnormality detecting circuit includes a phase shift detection part that detects a phase shift between an output voltage and an output current which are applied from the inverter to the load and sends an abnormal load signal based on the detected phase shift. The switching element including a self-arc-extinguishing element and a reflux diode connected in reversely parallel to the self-arc-extinguishing element. The phase shift detection part detects advance and delay of a phase of the output current with respect to the output voltage.

A load abnormality detecting circuit for an inverter to detect abnormality of a load during an operation of the inverter which has a switching element and a phase synchronizing loop controlling an output frequency to be a resonance frequency of the load, the load abnormality detecting circuit includes a phase shift detection part that detects a phase shift between an output voltage and an output current which are applied from the inverter to the load and sends an abnormal load signal based on the detected phase shift. The switching element including a self-arc-extinguishing element and a reflux diode connected in reversely parallel to the self-arc-extinguishing element. The phase shift detection part detects advance and delay of a phase of the output current with respect to the output voltage.

A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.

A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

A chip with power-glitch detection is provided, which includes a power terminal receiving power, an inverter, and a back-up power storage device coupled to the power terminal. The inverter has an input terminal coupled to the power terminal. The back-up power storage device transforms the power to back-up power. The inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the inverter.

Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.