A storage element that is operable based on a system clock signal, the storage element including a clock gating circuitry configured to generate a gated clock signal based on at least one Boolean signal and the system clock signal or a preprocessed system clock signal, wherein the clock gating circuitry comprises physical connections of small capacitance such that tapping of at least one of the physical connections results in a hold-time violation. Also, a hardware-based cryptography accelerator or a secured processing system including at least one such storage element, and a method for operating at least one storage element.

A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.

A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.

A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

A load circuit includes a first resistive element, a first transistor and a tristate control circuit. The first transistor has a first control terminal, a first connection terminal and a second connection terminal. The first connection terminal is coupled to to one of a first amplifier output terminal and a connection node through the first resistive element. The second connection terminal is coupled to the other of the first amplifier output terminal and the connection node. The tristate control circuit has a signal output terminal coupled to the first control terminal. When the signal output terminal is in the low impedance state, the first control terminal is arranged to receive a first control signal outputted from the signal output terminal. When the signal output terminal is in the high impedance state, the first control terminal is arranged to receive a second control signal different from the first control signal.

The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.