Patent classifications
H03K3/354
OSCILLATOR CIRCUIT, DEVICE AND METHOD FOR GENERATING AN OSCILLATOR SIGNAL
An oscillator circuit includes a current controller, a first capacitor and a second capacitor. A current generator is coupled to the current controller, the first and the second capacitor, and is operable, under control of a control signal of the current controller, provide charging currents. A comparator stage comprises a first input coupled to the first capacitor, a second input coupled to the second capacitor and a reference input to be supplied with the reference voltage. The comparator stage further includes an oscillator output to provide a clock signal based on a comparison of the capacitor voltages and the reference voltage, respectively. A modulation circuit comprises an oscillator input to input the clock signal, a reference output is connected to the current generator, and is operable to alternate between the charging currents, such that a charging current is provided as reference current at the reference output and at least one charging current is provided to alternately charge/discharge the first capacitor and the second capacitor to respective capacitor voltages.
OSCILLATOR CIRCUIT, DEVICE AND METHOD FOR GENERATING AN OSCILLATOR SIGNAL
An oscillator circuit includes a current controller, a first capacitor and a second capacitor. A current generator is coupled to the current controller, the first and the second capacitor, and is operable, under control of a control signal of the current controller, provide charging currents. A comparator stage comprises a first input coupled to the first capacitor, a second input coupled to the second capacitor and a reference input to be supplied with the reference voltage. The comparator stage further includes an oscillator output to provide a clock signal based on a comparison of the capacitor voltages and the reference voltage, respectively. A modulation circuit comprises an oscillator input to input the clock signal, a reference output is connected to the current generator, and is operable to alternate between the charging currents, such that a charging current is provided as reference current at the reference output and at least one charging current is provided to alternately charge/discharge the first capacitor and the second capacitor to respective capacitor voltages.
SPIKE GENERATION CIRCUIT, INFORMATION PROCESSING CIRCUIT, POWER CONVERSION CIRCUIT, DETECTOR, AND ELECTRONIC CIRCUIT
A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.
RC oscillating circuit
The disclosure discloses an RC oscillating circuit. A first end of a capacitor is grounded, a second end of the capacitor is connected to a charging path, a discharging path and a comparator, A first input end of a comparator is connected to first reference voltage. An output end of the comparator outputs a first output signal and is connected to a control end of the discharging path. The first reference voltage provides the flipped voltage of the comparator The first output signal forms an output clock signal. A first regulating circuit is configured to regulate the magnitude of the charging current and realize coarse frequency tuning. A second regulating circuit is configured to regulate the magnitude of the first reference voltage and realize fine frequency tuning. The disclosure has the advantages of low power consumption, fast start, high precision and wide tuning range.
RC oscillating circuit
The disclosure discloses an RC oscillating circuit. A first end of a capacitor is grounded, a second end of the capacitor is connected to a charging path, a discharging path and a comparator, A first input end of a comparator is connected to first reference voltage. An output end of the comparator outputs a first output signal and is connected to a control end of the discharging path. The first reference voltage provides the flipped voltage of the comparator The first output signal forms an output clock signal. A first regulating circuit is configured to regulate the magnitude of the charging current and realize coarse frequency tuning. A second regulating circuit is configured to regulate the magnitude of the first reference voltage and realize fine frequency tuning. The disclosure has the advantages of low power consumption, fast start, high precision and wide tuning range.
OSCILLATION CIRCUIT, DISTANCE MEASURING DEVICE, AND DISTANCE MEASURING METHOD
An oscillation circuit (10) includes a plurality of oscillators (11) and a wiring (12) that connects the plurality of oscillators (11). The wiring (12) is arranged so as to form a closed path that passes through once each of the plurality of oscillators (11). The plurality of oscillators (11) is arranged such that impedance viewed from each of the plurality of oscillators in the closed path satisfies a predetermined condition.
Relaxation oscillator and method
A relaxation oscillator and a method of controlling the relaxation oscillator are disclosed. The relaxation oscillator includes a reference voltage generating circuit configured to generate a reference voltage based on a transistor-based resistor, a variable voltage generating circuit configured to generate a variable voltage based on the reference voltage and a control switch, a threshold voltage generating circuit configured to generate a threshold voltage using a switched-capacitor resistor circuit, and a switch control circuit configured to output a control signal to control the control switch based on the variable voltage and the threshold voltage.
Relaxation oscillator and method
A relaxation oscillator and a method of controlling the relaxation oscillator are disclosed. The relaxation oscillator includes a reference voltage generating circuit configured to generate a reference voltage based on a transistor-based resistor, a variable voltage generating circuit configured to generate a variable voltage based on the reference voltage and a control switch, a threshold voltage generating circuit configured to generate a threshold voltage using a switched-capacitor resistor circuit, and a switch control circuit configured to output a control signal to control the control switch based on the variable voltage and the threshold voltage.
Ring oscillator with stages implemented to assess PFET-NFET process performance
An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.
Ring oscillator with stages implemented to assess PFET-NFET process performance
An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.