According to one embodiment of an asynchronous communication device, the transmitter circuit includes a signal generation circuit to output a first pulse signal and a delay compensation circuit to receive the first pulse signal, perform delay compensation processing on the pulse width of the first pulse signal, and output a second pulse signal obtained by the delay compensation processing. The delay unit receives the second pulse signal, causes delay in the rising or falling edge of the second pulse signal, and outputs a third pulse signal in which the delay is caused. The receiver circuit receives the third pulse signal and performs signal processing based on the third pulse signal. The delay compensation circuit, while maintaining the pulse period of the first pulse signal, performs pre-compensation processing on the first pulse signal based on a delay value of the delay to be caused by the delay unit.

Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

The disclosure relates to a method for operating a pulse generator for generating measuring pulses for a capacitive sensor having an adjustable pulse time in the range from 10 ns to 200 ns, having a controllable delay circuit which contains a first integrating RC combination (RT1/CT1) and a second integrating RC combination (RT2/CT2), having a logical combining element having two inputs and one output, an initialization circuit and a control unit, wherein the first input of the logical combining element receives a clock signal, and the second input of the logical combining element receives an analog setting signal (SSE) from the output of the delay circuit, wherein two simultaneous clock signals are generated, of which the first clock signal (T) is led without delay to the first input of the logical combining element, and the second clock signal (T2), delayed by the delay circuit, is led to the second input of the logical combining element, time-variable output pulses are generated with the aid of time-variable preloading signals (VL), wherein the output from the delay circuit after each measuring pulse is discharged or charged by the initialization switch.

A method for controlling a load-current zero-crossing of a switching regulator having a high-side switch and a low-side switch includes detecting, by a spike detection circuit, a presence of a spike on an output voltage of the switching regulator, determining, by the spike detection circuit, in the event that a spike is present, whether the spike is a positive spike or a negative spike, and adjusting a turn-off timing of the low-side switch based on a determination result.

An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.

An analog-based architecture is used to produce tap spacings in an n-tap UI-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve UI-spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the UI spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

A control device for a switching voltage regulator having a high-side switch and a low-side switch to supply a switching voltage to a load includes a comparator configured to compare the switching voltage with a reference voltage to provide an enable signal to the low-side switch, and a spike detection circuit configured to receive the switching voltage and output an offset control signal to execute a time shift to the enable signal.

Some embodiments include apparatuses comprising a first node; a second node; a first transistor and a second transistor, the first and second transistors including a common gate coupled to the node and a common terminal coupled to the second node; first additional transistors coupled in parallel with each other between a terminal of the first transistor and a first supply node, the first additional transistors including gates; and second additional transistors coupled in parallel with each other between a terminal of the second transistor and a second supply node, the second additional transistors including gates.

An impulse voltage generation device comprises: a high voltage generator to generate high DC voltage; a capacitor that is disposed in parallel to the high voltage generator and can be charged to a high voltage state; a power semiconductor switch that is placed at an output side of the high voltage generator and in series to the high voltage generator and is designed to shut off or allow electricity output from the high voltage generator; a function generator to output changes over time of impulse voltage to be applied to the test target; a current detector to detect output current; and an overcurrent protection circuit that is configured to conduct analog-to-digital conversion at sampling intervals sufficiently shorter than the application intervals when receiving a current signal from the current detector, monitors values of the output current, and to block output from the function generator to the power semiconductor switch if it is determined that there is an abnormality.