A delay device and a delay control method are provided. The delay device includes at least one current-controlled delay group and at least one switch. The at least one current-controlled delay group is coupled to a transmission wire, each of the at least one current-controlled delay group includes at least one current-controlled delayer, and each of the at least one current-controlled delayer provides a delay according to a control voltage. The at least one switch is coupled between the at least one current-controlled delay group and the transmission wire, and each of the at least one switch is turned on or off according to a bit of an enable signal applied thereto. In the disclosure, the generated delay can be dynamically adjusted and cannot be affected by parasitic capacitance.

This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.

An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.

This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.

A delay device and a delay control method are provided. The delay device includes at least one current-controlled delay group and at least one switch. The at least one current-controlled delay group is coupled to a transmission wire, each of the at least one current-controlled delay group includes at least one current-controlled delayer, and each of the at least one current-controlled delayer provides a delay according to a control voltage. The at least one switch is coupled between the at least one current-controlled delay group and the transmission wire, and each of the at least one switch is turned on or off according to a bit of an enable signal applied thereto. In the disclosure, the generated delay can be dynamically adjusted and cannot be affected by parasitic capacitance.

A device includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each of which receives a data input signal and generates a first data output signal. Each receiver includes a delay line that is devoid of a duty cycle corrector (DCC), that has a predetermined number of delay elements, and that introduces a propagation delay to the data input signal by a fixed amount that substantially matches a propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to a data signal-receiving device.

An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.