A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.

In some examples, a circuit is described. The circuit may be included in a digital phase-locked loop (PLL) and may include a first delay cell, a second delay cell, and a delay controller. The first delay cell may include a first inverter circuit that includes first and second transistors and may be configured to receive and to delay a first signal. The delay of the first inverter circuit may be based on first and second voltages respectively provided to the first and second transistors. The second delay cell may include a second inverter circuit that includes third and fourth transistors and may be configured to receive and to delay a second signal. The delay of the second inverter circuit may be based on third and fourth voltages respectively provided to the third and fourth transistors. The delay controller may be configured to provide the first, second, third, and fourth voltages.

Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.

According to one implementation, a computer system includes processing unit circuitry of one or more computer devices that include a plurality of transistors configured to a first voltage threshold, and digital voltage sensor circuitry (160) of the one or more computer devices that include at least a delay line circuit (126) including one or more digital gates (120A-N). Each of the one or more digital gates (120A-N) includes driving transistors configured to a second voltage threshold, where the digital voltage sensor circuit (160) is configured to predict voltage droop of the processing unit circuitry.

A delay cell includes two serial stacks of transistors. Each serial stack includes a PMOS transistor having a source coupled to a power supply node for a power supply voltage and includes an NMOS transistor having a source coupled to ground. In each serial stack, at least one diode-connected transistor is coupled between a drain of the PMOS transistor and a drain of the NMOS transistor.

An output control circuit and a voltage output circuit are provided. The output control circuit includes: a first output terminal and a second output terminal connected to a first switch and a second switch respectively, an input terminal, a first level shift circuit, a delay circuit that outputs a signal received after a delay time set longer than a delay time of the first level shift circuit, a second level shift circuit that level-shifts a signal received by an input port connected to an output port of the delay circuit and outputs a level-shifted signal, and a control circuit that outputs a signal with a signal level determined to be either a first level or a second level based on signal levels of signals received from two input ports.

The present description concerns a random number generation circuit (2) of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO1, R02) implemented in CMOS-on-FDSOI technology; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other one of the two oscillators (RO2) and delivering a corresponding binary signal (Beat); and a circuit (200) controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, RO2) based on a period difference between the two oscillators (RO1, RO2).

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.

Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.