A delay circuit with bias temperature instability (BTI) mitigation includes an input node; an output node configured to provide a delayed output signal that is a delayed representation of an input signal; a first inverter stage including a first complementary metal-oxide-semiconductor (CMOS) inverter and a resistive-capacitive (RC) delay circuit configured to provide an RC delay for a signal transition of the input signal, wherein the RC delay circuit includes a resistive network of transistors coupled between a first p-channel metal-oxide-semiconductor (PMOS) transistor and a first n-channel metal-oxide-semiconductor (NMOS) transistor of the first CMOS inverter; a second inverter stage including a second CMOS inverter coupled between the first inverter stage and the output node; and a supply cutoff circuit configured to disconnect the resistive network of transistors and/or the second CMOS inverter from respective voltage supplies based on one or more supply cutoff conditions being satisfied.

A memory device, comprising a phase split circuit configured to generate a first clock signal and a second clock signal used in an input/output circuit. The phase split circuit including, a first delay path configured to output a first delay signal; a second delay path configured to output a second delay signal; a third delay path configured to output a third delay signal; and a fourth delay path configured to output a fourth delay signal. The phase split circuit also includes: a first output terminal configured to phase-interpolate the first delay signal and the second delay signal to output the first clock signal; and a second output terminal configured to combine the third delay signal and the fourth delay signal to output the second clock signal complementary to the first clock signal.

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.