A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

The arrival time of an asynchronous signal from an asynchronous domain at a synchronizer circuit of a synchronous domain is modified by injecting synchronous domain timing into an additional last stage of the asynchronous logic function generating the asynchronous signal. That reduces the probability of metastability by increasing the probability that the asynchronous signal will arrive at the synchronizer at a time that can guarantee the setup time for the flip-flop(s) of the synchronizer.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.

In a control apparatus for a power converter, a current obtainer obtains a current flowing through an inductor as an inductor current, and an alternating-current voltage obtainer obtains an alternating-current voltage. A drive signal outputting unit generates, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command. The drive signal outputting unit performs peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command. A delay unit delays, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage. The drive signal defines the off-switching timing of the switch.

A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

An electronic device includes a unit interval detector including a plurality of delay cells and that receives a first signal, a second signal, and a third signal and detects a code indicating a unit interval from the first signal, the second signal, and the third signal, a clock recovery circuit that generates a clock signal from the first signal, the second signal, and the third signal in response to the code, and a data recovery circuit that generates a first receive signal, a second receive signal, and a third receive signal from the first signal, the second signal, and the third signal in response to the code and the clock signal. A total delay amount of the delay cells is smaller than a length of the unit interval and the unit interval detector performs a multi-stage detection operation including coarse detection and fine detection by using the delay cells.