A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.

In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

A timing data acquisition device includes a data signal generator, which is configured to generate a plurality of data signals by repeatedly delaying a first periodic timing signal in increments of a first delay value, and a clock signal generator, which is configured to generate a plurality of clock signals by repeatedly delaying a second periodic timing signal in increments of a second delay value exceeding the first delay value. A plurality of D flip-flops are also provided. The flip-flops have: (i) data terminals responsive to respective ones of the plurality of data signals, and (ii) clock terminals responsive to respective ones of the plurality of clock signals. The flip flops are configured to generate a plurality of latched output signals having values that collectively encode at least one of a set-up time and a hold-time of a semiconductor device by identifying a pass/fail boundary point between the delays associated with the plurality of data signals and the delays associated with the plurality of clock signals.

Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

In a control apparatus for a power converter, a current obtainer obtains a current flowing through an inductor as an inductor current, and an alternating-current voltage obtainer obtains an alternating-current voltage. A drive signal outputting unit generates, based on the alternating-current voltage obtained by the voltage obtainer, a sinusoidal command. The drive signal outputting unit performs peak-current mode control to output a drive signal that controls switching of the drive switch to thereby cause the inductor current to follow the sinusoidal command. A delay unit delays, for one switching cycle of the drive switch, an off-switching timing of the drive switch in accordance with the alternating-current voltage. The drive signal defines the off-switching timing of the switch.

A phase correction circuit, a phase correction method and an electric energy metering device are provided. The phase correction circuit includes a reference voltage circuit and a current correction circuit. The reference voltage circuit includes a first predetermined number of first delay D flip-flops and a first synchronization D flip-flop. The current correction circuit includes a second predetermined number of second delay D flip-flops, a second synchronization D flip-flop and a data selector. The data selector outputs a current signal of one of the second delay D flip-flops to the second synchronization D flip-flop. The second predetermined number is greater than or equal to the first predetermined number. In a case that the second predetermined number is equal to the first predetermined number, each of the second predetermined number and the first predetermined number is greater than 1.

Devices and methods for error checking transmissions include using error checking circuitry configured to receive a clock and reset. The error checking circuitry (ECC) includes an input counter configured to receive the clock and to count out multiple input clocks from the received clock. The ECC also includes a delay model configured to receive the clock and to output a delayed clock. Also, the ECC includes an output counter configured to receive the delayed clock and to count out multiple output clocks from the received delayed clock. Furthermore, the ECC includes multiple error calculation circuits arranged in parallel that each are configured to: receive data based on a respective input clock, generate an error indicator based on the received data with the error indicator indicating whether an error exists in the received data, and output the error indicator based at least in part on a respective output clock.