A data decoding method and device as well as an intelligent cipher key token are provided. The data decoding method includes: receiving a sinusoidal wave via an audio interface, wherein the sinusoidal wave has a waveform with at least one period, and different periods represent different bit values; processing the sinusoidal wave so as to obtain a first square wave, wherein the first square wave carries data to be decoded; determining whether there is a glitch waveform in the first square wave, based on a preset threshold or based on an adaptive threshold, wherein the adaptive threshold is calculated according to synchronization head data carried in the sinusoidal wave; if there is a glitch waveform in the first square wave, eliminating the glitch waveform from the first square wave so as to obtain a second square wave; and decoding the second square wave so as to obtain decoded data.

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

A broadband power limiter having a distributed architecture of multiple segments of self-actuating, adjustable power limiters, where the limiter segments are separated from each other along a signal path by intermediate matching inductors. The intermediate matching inductors are chosen to form, in combination with the capacitances of the limiter segments, an impedance matched, low-loss, broadband transmission line. Optionally, limiter segments may be configured with different sizes and stack depths in a tapered architecture, such that different limiter segments have different power limiting response times and power handling capabilities. As each limiter segment initiates its power limiting action, power is reflected back toward the signal line, helping to trigger the power limiting action of the remaining limiter segments. Optionally, a power detector circuit may provide a more ideal limiting function by modulating the threshold power point of the limiter segments as a function of the transient signal voltage.

A broadband power limiter having a distributed architecture of multiple segments of self-actuating, adjustable power limiters, where the limiter segments are separated from each other along a signal path by intermediate matching inductors. The intermediate matching inductors are chosen to form, in combination with the capacitances of the limiter segments, an impedance matched, low-loss, broadband transmission line. Optionally, limiter segments may be configured with different sizes and stack depths in a tapered architecture, such that different limiter segments have different power limiting response times and power handling capabilities. As each limiter segment initiates its power limiting action, power is reflected back toward the signal line, helping to trigger the power limiting action of the remaining limiter segments. Optionally, a power detector circuit may provide a more ideal limiting function by modulating the threshold power point of the limiter segments as a function of the transient signal voltage.

A time-of-flight laser distance device includes a laser transmitter, a laser pulse return detector to receive reflected laser pulses, and comparators with respective first and second trip levels. A preliminary distance to a target is based on a linear ramp as a function of lapsed time from laser pulse generation through an effective time period wherein an associated return pulse is detected. Time-of-flight values associated with a leading edge of the return pulse are obtained at each of the first and second trip levels. A time difference is determined between the obtained values, and a correction factor is applied with respect to the preliminary measured distance based on the determined time difference. A dual ADC may be used wherein the leading edge of the return pulse is calculated by measuring a slope associated with the time-of-flight values and extrapolating a slope origin to a zero crossing point.

A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE.sub.1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE.sub.2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.

A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE.sub.1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE.sub.2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.

The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.

A voltage detector for detecting whether an input voltage is no lower than a predetermined threshold voltage, includes a reference voltage generator configured to generate a reference voltage, and a comparator configured to receive the input voltage and the reference voltage and to detect whether the input voltage is no lower than the threshold voltage that is determined by the reference voltage. Here, the reference voltage generator includes a first write MOS transistor, a second write MOS transistor, a first output MOS transistor and a second output MOS transistor each including a control gate and a floating gate.