An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

A delay interpolator includes pull-up devices coupled between a supply rail and a node, pull-down devices coupled between the node and a ground, and a first control circuit coupled to the pull-up devices, wherein the first control circuit is configured to receive a first signal, a second signal, and a first delay code, input the first signal to a programmable number of the pull-up devices based on the first delay code, and input the second signal to remaining ones of the pull-up devices. The delay interpolator also includes a second control circuit coupled to the pull-down devices, wherein the second control circuit is configured to receive the first signal, the second signal, and a second delay code, input the first signal to a programmable number of the pull-down devices based on the second delay code, and input the second signal to remaining ones of the pull-down devices.

A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.

A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.