Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

Apparatus and methods for radio frequency (RF) switch control are provided. In certain embodiments, a level shifter for an RF switch includes a first level-shifting n-type transistor, a first cascode n-type transistor in series with the first level-shifting n-type transistor between a negative charge pump voltage and a first output that provides a first switch control signal, a first level-shifting p-type transistor, a first cascode p-type transistor in series with the first level-shifting p-type transistor between a positive charge pump voltage and the first output, and a second cascode p-type transistor between a regulated voltage and a gate of the first level-shifting n-type transistor and controlled by a first switch enable signal.

A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.

A switch control circuit includes: a clock generating circuit that generates one or more periodic signals having a predetermined cycle; a clock adjusting circuit that generates one or more control signals by adjusting a bias voltage of the one or more periodic signals and changing an ON period of the one or more periodic signals; and at least one switching circuit including one or more switches that are switched to ON if respective amplitudes of the generated one or more control signals is equal to or higher than a threshold value and that are switched to OFF if the respective amplitudes of the generated one or more control signals is less than the threshold value.

Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition processin lieu of a lithography processthereby providing for high speed operation and low cost manufacturing.

A semiconductor device including a bus master that receives a clock; a first bus slave that receives a first slave clock and has a first number of waits, and a second bus slave that receives a second slave clock and has a second number of waits, wherein the second number of waits is higher than the first number of waits, and wherein a phase difference between the clock and the first slave clock is higher than a phase difference between the clock and the second slave clock.

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves. A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.