Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

An embodiment of the present invention discloses a gate drive circuit comprising several stages of unit circuits, wherein each unit circuit comprises: a high level terminal, a low level terminal, a first clock terminal, a second clock terminal, a gate output terminal, a logic turn-on input terminal, a logic turn-on output terminal, a control module, a first gating module and a second gating module. An embodiment of the present invention also provides a display device comprising the gate drive circuit. A gate drive circuit with interlaced output is realized, ensuring no suspended state in time sequence between interlaced lines, while maintaining an original dual time sequence (i.e., eliminating suspended state between interlaced lines, and ensuring a stable output of the shifting register).

A clock transmission circuit includes a plurality of circuit regions that have common circuit patterns and are arranged along one direction. Each of the circuit patterns of the plurality of circuit regions has at least two circuit elements that are switchable between a high impedance state and a pass state, and wirings that are connected to the circuit patterns of circuit regions adjacent to concerned circuit region, among the plurality of circuit regions. States of the at least two circuit elements of the plurality of circuit regions are controlled to be predetermined states determined for each circuit region, so that at least a part of a clock tree crossing the plurality of circuit regions is configured.

A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. The second clock generator may generate a multi-phase clock signal from a second clock signal. The common mode generator may generate a reference voltage based on the first and second clock signals.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

An electronic device includes multiple functional logic modules each having a corresponding settling time, a clock generator element, and multiple memory elements. The clock generator element generates multiple clock signals having clock periods of a common duration. Each clock signal has a first clock transition and a second clock transition during each clock period, and a latest second clock transition of the clock signals in a particular clock period precedes an earliest first clock transition in a subsequent clock period by the settling time. Each memory element is clocked by a respective one of the clock signals, and each memory element includes an input latch clocked on a first clock transition of the respective one of the clock signals, and an output latch clocked on a second clock transition of the respective one of the clock signals.

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.