A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.

Circuitry for controlling a non-overlap time for a first switch and a second switch is described. Within a first state, the first switch is closed and the second switch is open, and within a second state, the first switch is open and the second switch is closed. The control circuitry has a first auxiliary switch and a second auxiliary switch. The control circuitry determines whether during a transition from the first state to the second state a current has flown through the serial arrangement of the first and second auxiliary switches. The control means adapts a non-overlap time between the first and second control signals for controlling a following transition from the first state to the second state, dependent on whether during said transition between the first and second states a current has flown through the serial arrangement of the first and second auxiliary switches.

Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.

Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.

The invention relates to a compensator device for compensating signal dependent delay variations, including dead time and reverse recovery time, causing un-linearity in a Class-D amplifier where the compensator device comprises: a first input terminal for receiving an input pulse width modulated input PWM signal comprising pulses with falling flanks corresponding to a falling level transition and rising flanks corresponding to a rising level transition; and a second input terminal configured to receive the signal provided at an output switching node of a Class-D amplifier; an output terminal for providing a compensated output signal; and controllable delay means configured to receive and delay the pulse modulated input signal, thereby providing a delayed version of the input signal to said output terminal of the compensator device. The compensator device further comprises time measuring means configured for measuring the time between a transition of the signal provided at the output terminal of the compensator device and the corresponding transition of the signal at the output switching node of a Class-D amplifier and based on these measurements providing a control signal to the controllable delay means. An advantageous effect of the present invention is that the rising and falling level transition delays will be substantially similar thus substantially removing non-linearity and obtaining substantially correct pulse widths. The invention further relates to a corresponding method, a driver device and a Class-D amplifier.

An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.

Techniques are provided to tune a gate-drive control signal for a switching device. In an aspect, a device is provided that includes a dead-time generator circuit, a first dead-time tuner circuit and a second dead-time tuner circuit. The dead-time generator circuit generates a control signal for a first switching device that is coupled to a second switching device via a switching node. The first dead-time tuner circuit generates, based on the control signal and a switching signal indicative of a voltage associated with the switching node, a first modified control signal for the first switching device. The second dead-time tuner circuit generates, based on a modified version of the switching signal and a tuning process that repeatedly modifies the control signal until a first dead-time value satisfies a defined criterion, a second modified control signal for the first switching device.