A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.

The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.

Disclosed is an electronic circuit for controlling a half H bridge, the half split H bridge including first and second MOSFET transistors of different respective types, with sources connected respectively to a supply line and to an electric mass, and with respective drains connected to a load. Moreover, the control circuit includes first and second bipolar transistors of different respective types, with collectors connected to the supply line and to the electric mass, respectively, and with respective bases connected to a control module for controlling the MOSFET transistors, as well as first and second arms mounted parallel relative to one another between the gates of the MOSFET transistors, connected to the emitter of the first bipolar transistor and of the second bipolar transistor, respectively, the first arm including a first diode and a first resistor, and the second arm including a second diode and a second resistor.

A dead time circuit (750) for a switching circuit is disclosed. The dead-time circuit comprises: an input (752) for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs (754a, 754b); a first feedforward path (756) coupled to the first output and arranged to receive the switching signal; a second feedforward path (758) coupled to the second output and arranged to receive the switching signal; a first feedback path (760) forming a first feedback loop between the first output and the second feedforward path; and a second feedback path (762) forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit (764a, 764b), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

A gate driver and a control method thereof are provided. The gate driver is coupled to a capacitor. The gate driver includes a timing control circuit and a switch unit. The switch unit is coupled to the timing control circuit, the capacitor and a working voltage. The timing control circuit receives an input control signal and performs a timing control to the input control signal to generate a first control signal and a second control signal. The switch unit includes a first switch element and a second switch element. The second switch element controls a body voltage of the first switch element according to the second control signal. The switch unit enables the working voltage to charge the capacitor via the switch unit according to the first control signal and the second control signal.

An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to translate an input signal in a first voltage domain to generate a complementary pair of first signals in a second voltage domain. The second circuit may be configured to logically switch the first signals to generate a complementary pair of second signals in the second voltage domain. The first signals may be logically switched such that both of the second signals are inactive before one of the second signals transitions from inactive to active. The third circuit may be configured to amplify the second signals to generate a complementary pair of output signals in the second voltage domain. Each of the output signals generally has a current capacity to drive one or more of a plurality of diodes in a diode switch circuit.

Techniques and devices for differential signal repeating are described. A differential signal repeating method may include receiving an input differential signal pair including first and second input signals received at first and second input terminals, respectively, and generating an output signal at an output terminal. Generating the output signal may include: based on a determination, at a first time, that the first and second input signals represent complementary values, setting a level of the output signal to represent an inverse of the value represented by the first input signal, and based on a determination, at a second time, that the first and second input signals do not represent complementary values, placing the output terminal in a high-impedance state.

Aspects of the disclosure provide a circuit. The circuit includes a voltage step up circuit, a voltage control unit, and a complementary voltage generator. The voltage step up circuit is configured to receive a primary supply voltage of a first voltage level and output a secondary supply voltage of a second voltage level that is higher than the first voltage level. The voltage control unit is configured to receive the secondary supply voltage and to output a control voltage having a voltage level in a range from a ground level to the second voltage level. The complementary voltage generator is configured to operate based on the primary supply voltage and to generate a pair of complementary signals in response to the control voltage. The voltage sum of the pair of complementary signals is equivalent to the first voltage level.

A dead time circuit (750) for a switching circuit is disclosed. The dead-time circuit comprises: an input (752) for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs (754a, 754b); a first feedforward path (756) coupled to the first output and arranged to receive the switching signal; a second feedforward path (758) coupled to the second output and arranged to receive the switching signal; a first feedback path (760) forming a first feedback loop between the first output and the second feedforward path; and a second feedback path (762) forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit (764a, 764b), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed.